Analog Devices ADuC812 - Manuals

Page 2 - USER INTERFACE TO OTHER ON-CHIP; TABLE OF CONTENTS

REV. B ADuC812 – 2 – FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ABSOLUTE MAXIMUM RATINGS . . ....

Page 3 - Unit; SPECIFICATIONS; to T

REV. B – 3 – ADuC812 ADuC812BS Parameter V DD = 5 V V DD = 3 V Unit Test Conditions/Comments ADC CHANNEL SPECIFICATIONS DC ACCURACY 3, 4 Resolution 12 12 Bits Integral Nonlinearity ± 1/2 ± 1/2 LSB typ f SAMPLE = 100 kHz ± 1.5 LSB max f SAMPLE = 100 kHz ± 1.5 ± 1.5 LSB typ f SAMPLE = 200 kHz Differen...

Page 4 - ADuC812–SPECIFICATIONS; ADuC812BS

REV. B – 4 – ADuC812–SPECIFICATIONS 1, 2 ADuC812BS Parameter V DD = 5 V V DD = 3 V Unit Test Conditions/Comments DAC AC CHARACTERISTICS Voltage Output Settling Time 15 15 µ s typ Full-Scale Settling Time toWithin 1/2 LSB of Final Value Digital-to-Analog Glitch Energy 10 10 nV sec typ 1 LSB Change at...

Page 5 - PSEN

REV. B – 5 – ADuC812 ADuC812BS Parameter V DD = 5 V V DD = 3 V Unit Test Conditions/Comments DIGITAL OUTPUTS Output High Voltage (V OH ) 2.4 V min V DD = 4.5 V to 5.5 V I SOURCE = 80 µ A 4.0 2.6 V typ V DD = 2.7 V to 3.3 V I SOURCE = 20 µ A Output Low Voltage (V OL ) ALE, PSEN , Ports 0 and 2 0.4 V ...

Page 6 - PIN CONFIGURATION; ORDERING GUIDE; ABSOLUTE MAXIMUM RATINGS

REV. B ADuC812 – 6 – PIN CONFIGURATION 52 51 50 49 48 43 42 41 40 47 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 13 12 11 39 38 37 36 35 34 33 32 31 30 29 28 27 PIN 1IDENTIFIER TOP VIEW (Not to Scale) P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 DV DD DGND P0.3/AD3 P0.2/AD2 P0.1/AD1 ...

Page 7 - PIN FUNCTION DESCRIPTIONS; Mnemonic

REV. B ADuC812 – 7 – PIN FUNCTION DESCRIPTIONS Mnemonic Type Function DV DD P Digital Positive Supply Voltage, 3 V or 5 V Nominal AV DD P Analog Positive Supply Voltage, 3 V or 5 V Nominal C REF I Decoupling Input for On-Chip Reference. Connect 0.1 µ F between this pin and AGND. V REF I/O Reference ...

Page 8 - TERMINOLOGY; Differential Nonlinearity

REV. B ADuC812 – 8 – Mnemonic Type Function PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external programmemory to the bus during external fetch operations. It is active every six oscillator periods except duringexternal data memory accesses. This pin r...

Page 9 - ARCHITECTURE, MAIN FEATURES; Figure 1. Program and Data Memory Maps; MEMORY ORGANIZATION; Figure 3. Programming Model

REV. B ADuC812 – 9 – ARCHITECTURE, MAIN FEATURES The ADuC812 is a highly integrated true 12-bit data acquisitionsystem. At its core, the ADuC812 incorporates a high- perfor-mance 8-bit (8052-Compatible) MCU with on-chipreprogrammable nonvolatile Flash program memory control-ling a multichannel (8-in...

Page 11 - SPECIAL FUNCTION REGISTERS; Figure 4. Special Function Register Locations and Reset Values

REV. B ADuC812 – 1 1 – SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general purpose register banks, reside in the special function register (SFR)area. The SFR registers include control, configuration and data registers that provide an interface between the CPU and...

Page 12 - Figure 5. ADC Transfer Function; Typical Operation; Figure 6. ADC Result Format

REV. B ADuC812 – 1 2 – ADC CIRCUIT INFORMATIONGeneral Overview The ADC conversion block incorporates a fast, 8-channel,12-bit, single supply A/D converter. This block provides theuser with multichannel mux, track/hold, on-chip reference,calibration features and A/D converter. All components in thisb...

Page 13 - EFH; EXC

REV. B ADuC812 – 1 3 – ADCCON1 – (ADC Control SFR #1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes asdetailed below. SFR Address: EFH SFR Power-On Default Value: 20H Table III. ADCCON1 SFR Bit Designations Bit Name Description ADCCON1...

Page 15 - Driving the A/D Converter; Figure 7. Internal ADC Structure; Op Amp Model; approaching

REV. B ADuC812 – 1 5 – Driving the A/D Converter The ADC incorporates a successive approximation (SAR) archi-tecture involving a charge-sampled input stage. Figure 7 showsthe equivalent circuit of the analog input section. Each ADCconversion is divided into two distinct phases as defined by theposit...

Page 16 - Figure 9. Decoupling V; and C; Figure 10. Using an External Voltage Reference; Configuring the ADC

REV. B ADuC812 – 1 6 – ground, no amplifier can deliver signals all the way to ground when powered by a single supply. Therefore, if a negative supply isavailable, you might consider using it to power the front-endamplifiers. If you do, however, be sure to include the Schottkydiodes shown in Figure ...

Page 17 - Figure 11. Typical DMA External Memory Preconfiguration; Micro Operation during ADC DMA Mode

REV. B ADuC812 – 1 7 – core. This mode allows the ADuC812 to capture a contiguoussample stream at full ADC update rates (200 kHz). A typical DMA Mode configuration example. To set the ADuC812 into DMA mode a number of steps mustbe followed. 1. The ADC must be powered down. This is done by ensuring M...

Page 18 - Calibration; Figure 14. Flash Memory Development; Flash/EE Memory and the ADuC812

REV. B ADuC812 – 1 8 – the gain calibration coefficient is divided into ADCGAINH (6 bits)and ADCGAINL (8 bits).The offset calibration coefficient compen-sates for dc offset errors in both the ADC and the input signal. Increasing the offset coefficient compensates for positive offset,and effectively ...

Page 19 - Parallel Programming; sing the Flash/EE Data Memory; Figure 16. User Flash/EE Memory Configuration; BCH to BFH respectively

REV. B ADuC812 – 1 9 – Using the Flash/EE Program Memory This 8K Byte Flash/EE Program Memory array is mappedinto the lower 8K bytes of the 64K bytes program space addres-sable by the ADuC812 and will be used to hold user code intypical applications. The program memory array can be programmed in one...

Page 20 - ECON—Flash/EE Memory Control SFR; Command Byte; Flash/EE Memory Timing; ETIM3 should always remain at its default value of 201 dec/C9 hex.

REV. B ADuC812 – 2 0 – ECON—Flash/EE Memory Control SFR This SFR acts as a command interpreter and may be writtenwith one of five command modes to enable various read, pro-gram and erase cycles as detailed in Table VII: Table VII. ECON–Flash/EE Memory Control RegisterCommand Modes Command Byte Comma...

Page 21 - DAC; DACCON; Bit; DAC Data Registers

REV. B ADuC812 – 2 1 – USER INTERFACE TO OTHER ON-CHIP ADuC812PERIPHERALS The following section gives a brief overview of the variousperipherals also available on-chip. A summary of the SFRs used tocontrol and configure these peripherals is also given. DAC The ADuC812 incorporates two 12-bit, voltag...

Page 22 - Using the D/A Converter; Figure 18. Resistor String DAC Functional Equivalent; except

REV. B ADuC812 – 2 2 – Using the D/A Converter The on-chip D/A converter architecture consists of a resistorstring DAC followed by an output buffer amplifier, the func-tional equivalent of which is illustrated in Figure 18. Details ofthe actual DAC architecture can be found in U.S. Patent Num-ber 59...

Page 23 - Figure 22. Buffering the DAC Outputs; Figure 23. DAC Output Spike at Chip Power-Up

REV. B ADuC812 – 2 3 – SOURCE/SINK CURRENT – mA 3 0 5 10 15 OUTPUT VOLTAGE – V 2 1 0 Figure 21. Source and Sink Current Capability withV REF = V DD = 3 V To drive significant loads with the DAC outputs, external buff-ering may be required, as illustrated in Figure 22. 9 ADuC812 10 Figure 22. Bufferi...

Page 24 - Set

REV. B ADuC812 – 2 4 – WATCHDOG TIMER The purpose of the watchdog timer is to generate a device resetwithin a reasonable amount of time if the ADuC812 entersan erroneous state, possibly due to a programming error.The Watchdog function can be disabled by clearing the WDE(Watchdog Enable) bit in the W...

Page 28 - C-COMPATIBLE INTERFACE; C Control Register; Table XIII. I2CCON SFR Bit Designations; C Address Register

REV. B ADuC812 – 2 8 – I 2 C-COMPATIBLE INTERFACE The ADuC812 supports a 2-wire serial interface mode which isI 2 C compatible. The I 2 C-compatible interface shares its pins with the on-chip SPI interface and therefore the user can only enableone or the other interface at any given time (see SPE in...

Page 29 - Pin; WR

REV. B ADuC812 – 2 9 – 8051-COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondaryperipheral circuits that are also available to the user on-chip.These remaining functions are fully 8051-compatible and arecontrolled via standard 8051 SFR bit definitions. Parallel...

Page 31 - Table XVII. TCON SFR Bit Designations; Timer/Counter 0 and 1 Data Registers

REV. B ADuC812 – 3 1 – 1 F T 1 R T 0 F T 0 R T 1 E I 1 1 T I 1 0 E I 1 0 T I 1 NOTE 1 These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins. Table XVII. TCON SFR Bit Designations Bit Name Descr...

Page 33 - Timer/Counter 2 Data Registers

REV. B ADuC812 – 3 3 – T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default Value 00H Bit Addressable Yes 2 F T 2 F X E K L C R K L C T 2 N E X E 2 R T 2 T N C 2 P A C Table XVIII. T2CON SFR Bit Designations Bit Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a ti...

Page 34 - MODE; Baud Rate

REV. B ADuC812 – 3 4 – Timer/Counter Operation Modes The following paragraphs describe the operating modes for timer/counter 2. The operating modes are selected by bits in the T2CONSFR as shown in Table XIX. Table XIX. TIMECON SFR Bit Designations RCLK (or) TCLK CAP2 TR2 MODE 0 0 1 16-Bit Autoreload...

Page 36 - Figure 32. UART Serial Port Transmission, Mode 0; Figure 33. UART Serial Port Transmission, Mode 0; The eight bits in the receive shift register are latched into SBUF.; Mode 0 Baud Rate Generation; The baud rate in Mode 0 is fixed:; Mode 2 Baud Rate Generation; Mode 1 and 3 Baud Rate Generation

REV. B ADuC812 – 3 6 – Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in theSFR SCON. Serial data enters and exits through RXD. TXDoutputs the shift clock. Eight data bits are transmitted or received.Transmission is initiated by any instruction that writes...

Page 37 - Timer 1 Generated Baud Rates; Timer 2 Generated Baud Rates

REV. B ADuC812 – 3 7 – Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud ratesin Modes 1 and 3 are determined by the Timer 1 overflow rate andthe value of SMOD as follows: Modes 1 and 3 Baud Rate = (2 SMOD /32) × ( Timer 1 Overflow Rate ) The Timer 1 interrupt sh...

Page 40 - Figure 35. External Parallel Resonant Crystal Connections; External Memory Interface; EA; Figure 37. External Program Memory Interface

REV. B ADuC812 – 4 0 – ADuC812 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design consider-ations that must be addressed when integrating the ADuC812into any hardware system. Clock Oscillator The clock source for the ADuC812 can come either from anexternal source or...

Page 41 - Power-On Reset Operation; Figure 40. External POR Timing; Figure 41. External Active High POR Circuit; Figure 42. External Active Low POR Circuit; Power Supplies; Figure 43. External Dual-Supply Connections

REV. B ADuC812 – 4 1 – If access to more than 64K bytes of RAM is desired, a featureunique to the ADuC812 allows addressing up to 16M bytesof external RAM simply by adding an additional latch as illustratedin Figure 39. LATCH ADuC812 RD P2 ALE P0 WR LATCH SRAM OE A8–A15 A0–A7 D0–D7(DATA) WE A16–A23 ...

Page 42 - Figure 44. External Single-Supply Connections; Power Consumption; total; Table XXVIII. Typical I; of Core and Peripherals

REV. B ADuC812 – 4 2 – As an alternative to providing two separate power supplies, theuser can help keep AV DD quiet by placing a small series resistor and/or ferrite bead between it and DV DD , and then decoupling AV DD separately to ground. An example of this configuration is shown in Figure 44. W...

Page 43 - Grounding and Board Layout Recommendations; since that would force; is usually; Figure 45. System Grounding Schemes

REV. B ADuC812 – 4 3 – Grounding and Board Layout Recommendations As with all high resolution data converters, special attention mustbe paid to grounding and PC board layout of ADuC812-baseddesigns in order to achieve optimum performance from the ADCsand DAC. Although the ADuC812 has separate pins f...

Page 44 - Figure 46. Typical System Configuration; OTHER HARDWARE CONSIDERATIONS

REV. B ADuC812 – 4 4 – C1+ V+ C1– C2+ C2– V– T2OUT R2IN V CC GND T1OUT R1IN R1OUT T1IN T2IN R2OUT ADM202 DV DD 27 34 33 31 30 29 28 39 38 37 36 35 32 40 47 46 44 43 42 41 52 51 50 49 48 45 DV DD 1k DV DD 1k 2-PIN HEADER FOREMULATION ACCESS(NORMALLY OPEN) DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) ...

Page 45 - Figure 48. Typical Debug Session

REV. B ADuC812 – 4 5 – Note that the serial port debugger is fully contained on theADuC812 device, (unlike “ROM monitor” type debuggers) andtherefore no external memory is needed to enable in-systemdebug sessions. Single-Pin Emulation Mode Also built into the ADuC812 is a dedicated controller forsin...

Page 46 - Figure 49. XTAL 1 Input; Figure 50. Timing Waveform Characteristics; TIMING SPECIFICATIONS

REV. B ADuC812 – 4 6 – (AV DD = DV DD = 3.0 V or 5.0 V 10%. All specifications T A = T MIN to T MAX unless otherwise noted.) 12 MHz Variable Clock Parameter Min Typ Max Min Typ Max Unit Figure CLOCK INPUT (External Clock Driven XTAL1) t CK XTAL1 Period 83.33 62.5 1000 ns 50 t CKL XTAL1 Width Low 20 ...

Page 47 - Figure 51. External Program Memory Read Cycle

REV. B ADuC812 – 4 7 – 12 MHz Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL PROGRAM MEMORY t LHLL ALE Pulsewidth 127 2t CK – 40 ns 52 t AVLL Address Valid to ALE Low 43 t CK – 40 ns 52 t LLAX Address Hold after ALE Low 53 t CK – 30 ns 52 t LLIV ALE Low to Valid Instruction In 234 4t ...

Page 48 - Figure 52. External Data Memory Read Cycle

REV. B ADuC812 – 4 8 – 12 MHz Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY READ CYCLE t RLRH RD Pulsewidth 400 6t CK – 100 ns 53 t AVLL Address Valid after ALE Low 43 t CK – 40 ns 53 t LLAX Address Hold after ALE Low 48 t CK – 35 ns 53 t RLDV RD Low to Valid Data In 252 ...

Page 49 - Figure 53. External Data Memory Write Cycle

REV. B ADuC812 – 4 9 – 12 MHz Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY WRITE CYCLE t WLWH WR Pulsewidth 400 6t CK – 100 ns 54 t AVLL Address Valid after ALE Low 43 t CK – 40 ns 54 t LLAX Address Hold after ALE Low 48 t CK – 35 ns 54 t LLWL ALE Low to RD or WR Low 200...

Page 50 - Figure 54. UART Timing in Shift Register Mode

REV. B ADuC812 – 5 0 – 12 MHz Variable Clock Parameter Min Typ Max Min Typ Max Unit Figure UART TIMING (Shift Register Mode) t XLXL Serial Port Clock Cycle Time 1.0 12t CK µ s 55 t QVXH Output Data Setup to Clock 700 10t CK – 133 ns 55 t DVXH Input Data Setup to Clock 300 2t CK + 133 ns 55 t XHDX In...

Page 51 - C-Compatible Interface Timing

REV. B ADuC812 – 5 1 – Parameter Min Max Unit Figure I 2 C-COMPATIBLE INTERFACE TIMING t L SCLOCK Low Pulsewidth 4.7 µ s 56 t H SCLOCK High Pulsewidth 4.0 µ s 56 t SHD Start Condition Hold Time 0.6 µ s 56 t DSU Data Setup Time 100 ns 56 t DHD Data Hold Time 0 0.9 µ s 56 t RSU Setup Time for Repeated...

Page 56 - Revision History; Location

REV. B – 5 6 – C00208–0–10/01(B) PRINTED IN U.S.A. ADuC812 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 52-Lead Plastic Quad Flatpack (S-52) TOP VIEW (PINS DOWN) PIN 1 1 40 52 26 27 13 14 39 SQ 0.557 (14.15)0.537 (13.65) 0.398 (10.11) 0.390 (9.91) SQ 0.014 (0.35)0.010 (0.25) 0.025 (0.65) ...