Analog Devices AD9912 - Manuals

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Manual

Manual Analog Devices AD9912

Summary

Page 2 - TABLE OF CONTENTS; REVISION HISTORY

AD9912 Rev. D | Page 2 of 40 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description .......................

Page 3 - SPECIFICATIONS; DC SPECIFICATIONS

AD9912 Rev. D | Page 3 of 40 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, AVSS = 0 V, DVSS = 0 V, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY VOLTAGE DVDD_I/O (Pin 1) 3.135 3.30 3.465...

Page 5 - AC SPECIFICATIONS

AD9912 Rev. D | Page 5 of 40 AC SPECIFICATIONS f S = 1 GHz, DAC R SET = 10 kΩ, unless otherwise noted. Power supply pins within the range specified in the DC Specifications section. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments FDBK_IN INPUT Pin 40, Pin 41 Input Frequency Range 10 400...

Page 7 - ABSOLUTE MAXIMUM RATINGS; Parameter; THERMAL RESISTANCE; is specified for the worst-case conditions, that is, a device; Table 4. Thermal Resistance; Unit; ESD CAUTION

AD9912 Rev. D | Page 7 of 40 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Analog Supply Voltage (AVDD) 2 V Digital Supply Voltage (DVDD) 2 V Digital I/O Supply Voltage (DVDD_I/O) 3.6 V DAC Supply Voltage (AVDD3 Pins) 3.6 V Maximum Digital Input Voltage −0.5 V to DVDD_I/O + 0.5 V Storage Temper...

Page 8 - PIN CONFIGURATION AND FUNCTION DESCRIPTIONS; Table 5. Pin Function Descriptions

AD9912 Rev. D | Page 8 of 40 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1INDICATOR 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC NC A V DD NC NC NC A V DD A V DD A V DD A V DD SYSC L K SYSC L K B A V DD A V DD LOOP _ FI L T ER CL KM O DE S E L 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 4...

Page 10 - TYPICAL PERFORMANCE CHARACTERISTICS; = 10 kΩ, unless otherwise noted. See Figure 26 for 1 GHz reference

AD9912 Rev. D | Page 10 of 40 TYPICAL PERFORMANCE CHARACTERISTICS AVDD, AVDD3, and DVDD at nominal supply voltage; DAC R SET = 10 kΩ, unless otherwise noted. See Figure 26 for 1 GHz reference phase noise used for generating these plots. 06763- 003 0 100 200 300 400 500 OUTPUT FREQUENCY (MHz) –50 –55...

Page 15 - INPUT/OUTPUT TERMINATION RECOMMENDATIONS

AD9912 Rev. D | Page 15 of 40 INPUT/OUTPUT TERMINATION RECOMMENDATIONS DOWNSTREAM DEVICE (HIGH-Z) AD9912 1.8V HSTL OUTPUT 100 Ω 06763- 027 0.01µF 0.01µF Figure 33. AC-Coupled HSTL Output Driver DOWNSTREAM DEVICE (HIGH-Z) AD9912 1.8V HSTL OUTPUT 50 Ω 50 Ω 06763- 028 AVDD/2 Figure 34. DC-Coupled HSTL ...

Page 16 - THEORY OF OPERATION; OVERVIEW; is

AD9912 Rev. D | Page 16 of 40 THEORY OF OPERATION 06763- 031 DDS/DAC FREQUENCY TUNING WORD ÷S 2× DIGITAL SYNTHESIS CORE CONTROL LOGIC LOW NOISE CLOCK MULTIPLIER AMP SYSCLK PORT EXTERNAL ANALOG LOW-PASS FILTER EXTERNAL LOOP FILTER DIGITAL INTERFACE SYSCLK SYSCLKB S1 TO S4 FDBK_IN FDBK_INB DAC_OUT DAC...

Page 17 - FTW; phase; RECONSTRUCTION FILTER

AD9912 Rev. D | Page 17 of 40 06763- 032 DAC (14-BIT) ANGLE TO AMPLITUDE CONVERSION 14 19 19 48 48 48 14 PHASE OFFSET Q D 48-BIT ACCUMULATOR FREQUENCY TUNING WORD (FTW) f S DAC_RSET DAC_OUT DAC_OUTB DAC I-SET REGISTERS AND LOGIC Figure 40. DDS Block Diagram The input to the DDS is a 48-bit FTW that ...

Page 18 - third

AD9912 Rev. D | Page 18 of 40 PRIMARY SIGNAL FILTER RESPONSE SIN(x)/x ENVELOPE SPURS IMAGE 0 IMAGE 1 IMAGE 2 IMAGE 3 IMAGE 4 0 –20 –40 –60 –80 –100 MAGNITUDE (dB) f s /2 f s 3 f s /2 2 f s 5 f s /2 f BASE BAND 06763- 034 Figure 42. DAC Spectrum vs. Reconstruction Filter Response Because the DAC cons...

Page 19 - SYSCLK INPUTS; Functional Description; SYSCLK PLL bypassed; SYSCLK PLL Doubler

AD9912 Rev. D | Page 19 of 40 SYSCLK INPUTS Functional Description An external time base connects to the AD9912 at the SYSCLK pins to generate the internal high frequency system clock (f S ). The SYSCLK inputs can be operated in one of the following three modes: • SYSCLK PLL bypassed • SYSCLK PLL en...

Page 20 - SYSCLK PLL Multiplier; Multiplier

AD9912 Rev. D | Page 20 of 40 SYSCLK PLL Multiplier When the SYSCLK PLL multiplier path is employed, the frequency applied to the SYSCLK input pins must be limited so as not to exceed the maximum input frequency of the SYSCLK PLL phase detector. A block diagram of the SYSCLK generator appears in Fig...

Page 21 - Primary 1.8 V Differential HSTL Driver; HARMONIC SPUR REDUCTION

AD9912 Rev. D | Page 21 of 40 Note that the SYSCLK PLL bypassed and SYSCLK PLL enabled input paths are internally biased to a dc level of ~1 V. Care should be taken to ensure that any external connections do not disturb the dc bias because this may significantly degrade performance. Generally, it is...

Page 23 - THERMAL PERFORMANCE; Table 7. Thermal Parameters; PD

AD9912 Rev. D | Page 23 of 40 THERMAL PERFORMANCE Table 7. Thermal Parameters Symbol Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board Value Unit θ JA Junction-to-ambient thermal resistance, 0.0 m/sec air flow per JEDEC JESD51-2 (still air) 25.2 °C/W θ JMA Junction-to-ambient t...

Page 24 - DEFAULT OUTPUT FREQUENCY ON POWER-UP; frequencies scale 1:1 with f; Status Pin

AD9912 Rev. D | Page 24 of 40 POWER-UP POWER-ON RESET On initial power-up, the AD9912 internally generates a 75 ns RESET pulse. The pulse is initiated when both of the following two conditions are met: • The 3.3 V supply is greater than 2.35 V ± 0.1 V. • The 1.8 V supply is greater than 1.4 V ± 0.05...

Page 25 - POWER SUPPLY PARTITIONING; increases from 50 MHz to 400 MHz.

AD9912 Rev. D | Page 25 of 40 POWER SUPPLY PARTITIONING The AD9912 features multiple power supplies, and their power consumption varies with its configuration. This section covers which power supplies can be grouped together and how the power consumption of each block varies with frequency. The numb...

Page 26 - SERIAL CONTROL PORT; SERIAL CONTROL PORT PIN DESCRIPTIONS; (serial data out) is used only in the unidirectional I/O mode; OPERATION OF SERIAL CONTROL PORT; Framing a Communication Cycle with CSB

AD9912 Rev. D | Page 26 of 40 SERIAL CONTROL PORT The AD9912 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. Single or multiple byte transfers are supported, as well as MSB firs...

Page 27 - Read; The MSB of the instruction word is R/W; Table 9. Byte Transfer Count; Streaming mode; MSB/LSB FIRST TRANSFERS

AD9912 Rev. D | Page 27 of 40 Read If the instruction word is for a read operation (I15 = 1), the next N × 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1, 2, 3, or 4, as determined by [W1:W0]. In this case, 4 is used for streaming mode where four or...

Page 30 - Reserved

AD9912 Rev. D | Page 30 of 40 I/O REGISTER MAP All address and bit locations that are left blank in Table 12 are unused. Table 12. Addr (Hex) Type 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default (Hex) Serial port configuration and part identification 0x0000 Serial config. SDO active L...

Page 32 - I/O REGISTER DESCRIPTIONS; Register 0x0000—Serial Port Configuration

AD9912 Rev. D | Page 32 of 40 I/O REGISTER DESCRIPTIONS SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005) Register 0x0000—Serial Port Configuration Table 13. Bits Bit Name Description [7:4] These bits are the mirror image of Bits[3:0]. 3 Long instruction Read-only; the AD9912 supports o...

Page 34 - FREQUENCY TUNING WORD (REGISTER 0x01A0 TO REGISTER 0x01AD)

AD9912 Rev. D | Page 34 of 40 CMOS OUTPUT DIVIDER (S-DIVIDER) (REGISTER 0x0100 TO REGISTER 0x0106) Register 0x0100 to Register 0x0103—Reserved Register 0x0104—S-Divider Table 21. Bits Bit Name Description [7:0] S-divider CMOS output divider. Divide ratio = 1 − 65,536. If the desired S-divider settin...

Page 35 - Register 0x01AC—Phase; DDS phase word

AD9912 Rev. D | Page 35 of 40 Register 0x01A9—FTW0 (Frequency Tuning Word) (Continued) Table 27. Bits Bit Name Description [31:24] FTW0 These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio of the AD9912 output frequency to its DAC system clock. Register 0...

Page 36 - See the Harmonic Spur Reduction section.

AD9912 Rev. D | Page 36 of 40 DOUBLER AND OUTPUT DRIVERS (REGISTER 0x0200 TO REGISTER 0x0201) Register 0x0200—HSTL Driver Table 32. Bits Bit Name Description 4 OPOL Output polarity. Setting this bit inverts the HSTL driver output polarity. [3:2] Reserved Reserved. [1:0] HSTL output doubler HSTL outp...

Page 38 - OUTLINE DIMENSIONS

AD9912 Rev. D | Page 38 of 40 OUTLINE DIMENSIONS PIN 1INDICATOR TOP VIEW 8.75 BSC SQ 9.00 BSC SQ 1 64 16 17 49 48 32 33 0.500.400.30 0.50 BSC 0.20 REF 12° MAX 0.80 MAX0.65 TYP 1.000.850.80 7.50REF 0.05 MAX0.02 NOM 0.60 MAX 0.60 MAX *4.85 4.70 SQ4.55 EXPOSED PAD (BOTTOM VIEW) *COMPLIANT TO JEDEC STAN...

Page 39 - ORDERING GUIDE; Model; Evaluation Board

AD9912 Rev. D | Page 39 of 40 ORDERING GUIDE Model Temperature Range Package Description Package Option AD9912ABCPZ 1, 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-7 AD9912ABCPZ-REEL7 1, 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-7 AD9912BCPZ 1...

Page 40 - NOTES