Analog Devices ADSP-TS201S - Manuals

Page 2 - TABLE OF CONTENTS; Designing an Emulator-Compatible; REVISION HISTORY; Applied Corrections to:

Rev. C | Page 2 of 48 | December 2006 ADSP-TS201S TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Dual Compute Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Da...

Page 3 - GENERAL DESCRIPTION; Table 1; Benchmark; K point complex FFT; Cache preloaded; I/O DMA transfer rate; Figure 2. ADSP-TS201S Single-Processor System with External SDRAM

ADSP-TS201S Rev. C | Page 3 of 48 | December 2006 GENERAL DESCRIPTION The ADSP-TS201S TigerSHARC processor is an ultrahigh per-formance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual comp...

Page 4 - DUAL COMPUTE BLOCKS; Static Superscalar is a trademark of Analog Devices, Inc.

Rev. C | Page 4 of 48 | December 2006 ADSP-TS201S The TigerSHARC DSP uses a Static Superscalar TM † architecture. This architecture is superscalar in that the ADSP-TS201S pro-cessor’s core can execute simultaneously from one to four 32-bit instructions encoded in a very large instruction word (VLIW)...

Page 5 - PROGRAM SEQUENCER; Interrupt Controller; DSP MEMORY; Figure 3

ADSP-TS201S Rev. C | Page 5 of 48 | December 2006 The IALUs have hardware support for circular buffers, bit reverse, and zero-overhead looping. Circular buffers facilitate efficient programming of delay lines and other data structures required in digital signal processing, and they are commonly used...

Page 6 - INTERNAL S PACE; GLOBAL SPACE

Rev. C | Page 6 of 48 | December 2006 ADSP-TS201S 33.6G bytes per second, enabling the core and I/O to access eight 32-bit data-words and four 32-bit instructions each cycle. The DSP’s flexible memory structure enables: • DSP core and I/O accesses to different memory blocks in the same cycle • DSP c...

Page 7 - Host Interface; Multiprocessor Interface; Figure 4; SDRAM Controller; DMA CONTROLLER

ADSP-TS201S Rev. C | Page 7 of 48 | December 2006 The ADSP-TS201S processor provides programmable memory, pipeline depth, and idle cycle for synchronous accesses; and external acknowledge controls to support interfacing to pipe-lined or slow devices, host processors, and other memory-mapped peripher...

Page 8 - Figure 4. ADSP-TS201S Shared Memory Multiprocessing System

Rev. C | Page 8 of 48 | December 2006 ADSP-TS201S external memory. These transfers only use handshake mode protocol. DMA priority rotates between the four receive channels. • AutoDMA transfers. Two dedicated unidirectional DMA channels transfer data received from an external bus master to internal m...

Page 9 - RESET AND BOOTING; Table 2; CLOCK DOMAINS; Figure 5; Table 2. No Boot, Run from Memory Addresses; Figure 5. Clock Domains

ADSP-TS201S Rev. C | Page 9 of 48 | December 2006 LINK PORTS (LVDS) The DSP’s four full-duplex link ports each provide additional four-bit receive and four-bit transmit I/O capability, using low voltage, differential-signal (LVDS) technology. With the ability to operate at a double data rate—latchin...

Page 10 - POWER DOMAINS; FILTERING REFERENCE VOLTAGE AND CLOCKS; Figure 6; DEVELOPMENT TOOLS; Filtering Scheme

Rev. C | Page 10 of 48 | December 2006 ADSP-TS201S POWER DOMAINS The ADSP-TS201S processor has separate power supply con-nections for internal logic (V DD ), analog circuits (V DD_A ), I/O buffer (V DD_IO ), and internal DRAM (V DD_DRAM ) power supply. Note that the analog (V DD_A ) supply powers th...

Page 11 - EVALUATION KIT; Analog Devices offers a range of EZ-KIT Lite; ADDITIONAL INFORMATION; SHARC Processor Hardware Reference; EZ-Kit Lite is a registered trademark of Analog Devices, Inc.

ADSP-TS201S Rev. C | Page 11 of 48 | December 2006 eliminating the need to start from the very beginning when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, pre-emptive, ...

Page 12 - PIN FUNCTION DESCRIPTIONS; Table 3. Pin Definitions—Clocks and Reset; Table 4; For more information, see Clock

Rev. C | Page 12 of 48 | December 2006 ADSP-TS201S PIN FUNCTION DESCRIPTIONS While most of the ADSP-TS201S processor’s input pins are nor-mally synchronous—tied to a specific clock—a few are asynchronous. For these asynchronous signals, an on-chip syn-chronization circuit prevents metastability prob...

Page 13 - Table 5. Pin Definitions—External Port Bus Controls; Reset and Booting on

ADSP-TS201S Rev. C | Page 13 of 48 | December 2006 Table 5. Pin Definitions—External Port Bus Controls Signal Type Term Description ADDR31–0 I/O/T(pu_ad) nc Address Bus. The DSP issues addresses for accessing memory and peripherals on these pins. In a multiprocessor system, the bus master drives add...

Page 14 - Table 6. Pin Definitions—External Port Arbitration; Electrical Characteristics on Page 22

Rev. C | Page 14 of 48 | December 2006 ADSP-TS201S Table 6. Pin Definitions—External Port Arbitration Signal Type Term Description BR7–0 I/O V DD_IO 1 Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to arbitrate for bus mastership. Each DSP drives its own BRx line (corr...

Page 15 - Table 7. Pin Definitions—External Port DMA/Flyby

ADSP-TS201S Rev. C | Page 15 of 48 | December 2006 Table 7. Pin Definitions—External Port DMA/Flyby Signal Type Term Description DMAR3–0 I/A epu DMA Request Pins. Enable external I/O devices to request DMA services from the DSP. In response to DMARx, the DSP performs DMA transfers according to the D...

Page 16 - Table 8. Pin Definitions—External Port SDRAM Controller; Figure 3 on Page 6

Rev. C | Page 16 of 48 | December 2006 ADSP-TS201S Table 8. Pin Definitions—External Port SDRAM Controller Signal Type Term Description MSSD3–0 I/O/T(pu_0) nc Memory Select SDRAM. MSSD0, MSSD1, MSSD2, or MSSD3 is asserted whenever the DSP accesses SDRAM memory space. MSSD3–0 are decoded memory addre...

Page 17 - Table 9. Pin Definitions—JTAG Port; Reset and; See the reference

ADSP-TS201S Rev. C | Page 17 of 48 | December 2006 Table 9. Pin Definitions—JTAG Port Signal Type Term Description EMU O/OD nc 1 Emulation. Connected to the DSP’s JTAG emulator target board connector only. TCK I epd or epu 1 Test Clock (JTAG). Provides an asynchronous clock for JTAG scan. TDI I (pu_...

Page 18 - Table 11. Pin Definitions—Link Ports; Electrical Characteristics on

Rev. C | Page 18 of 48 | December 2006 ADSP-TS201S Table 11. Pin Definitions—Link Ports Signal Type Term Description LxDATO3–0P O nc Link Ports 3–0 Data 3–0 Transmit LVDS P LxDATO3–0N O nc Link Ports 3–0 Data 3–0 Transmit LVDS N LxCLKOUTP O nc Link Ports 3–0 Transmit Clock LVDS P LxCLKOUTN O nc Link...

Page 20 - STRAP PIN FUNCTION DESCRIPTIONS; Table 16. Pin Definitions—I/O Strap Pins

Rev. C | Page 20 of 48 | December 2006 ADSP-TS201S STRAP PIN FUNCTION DESCRIPTIONS Some pins have alternate functions at reset. Strap options set DSP operating modes. During reset, the DSP samples the strap option pins. Strap pins have an internal pull-up or pull-down for the default value. If a str...

Page 21 - ADSP-TS201S—SPECIFICATIONS; Link Port Low Voltage, Differential-Signal; OPERATING CONDITIONS; Ordering Guide on Page 46

ADSP-TS201S Rev. C | Page 21 of 48 | December 2006 ADSP-TS201S—SPECIFICATIONS Note that component specifications are subject to change with-out notice. For information on link port electrical characteristics, see Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timin...

Page 22 - ELECTRICAL CHARACTERISTICS; Table 18. Maximum Duty Cycle for Input Transient Voltage; Parameter Description; Applies to output and bidirectional pins.

Rev. C | Page 22 of 48 | December 2006 ADSP-TS201S ELECTRICAL CHARACTERISTICS Table 18. Maximum Duty Cycle for Input Transient Voltage V IN Max (V) 1 V IN Min (V) 1 Maximum Duty Cycle 2 +3.63 –0.33 100% +3.64 –0.34 90% +3.70 –0.40 50% +3.78 –0.48 30% +3.86 –0.56 17% +3.93 –0.63 10% 1 The individual ...

Page 23 - PACKAGE INFORMATION; The information presented in; ABSOLUTE MAXIMUM RATINGS; Figure 8. Typical Package Brand; Table 19. Package Brand Information; Table 20. Absolute Maximum Ratings; Applies to 10% transient duty cycle. For other duty cycles see

ADSP-TS201S Rev. C | Page 23 of 48 | December 2006 PACKAGE INFORMATION The information presented in Figure 8 provide details about the package branding for the ADSP-TS201S processors. For a com-plete listing of product availability, see Ordering Guide on Page 46 . ABSOLUTE MAXIMUM RATINGS Stresses g...

Page 24 - TIMING SPECIFICATIONS; General AC Timing; For output specifications on FLAG3–0 pins, see; ) divided by the system clock ratio

Rev. C | Page 24 of 48 | December 2006 ADSP-TS201S TIMING SPECIFICATIONS With the exception of DMAR3–0, IRQ3–0, TMR0E, and FLAG3–0 (input only) pins, all ac timing for the ADSP-TS201S processor is relative to a reference clock edge. Because input setup/hold, output valid/hold, and output enable/disa...

Page 25 - System clock transition times apply to minimum SCLK cycle time (t

ADSP-TS201S Rev. C | Page 25 of 48 | December 2006 Table 23. Reference Clocks—System Clock (SCLK) Cycle Time Parameter Description SCLKRAT = 4 × , 6 × , 8 × , 10 × , 12 × SCLKRAT = 5 × , 7 × Unit Min Max Min Max t SCLK 1, 2, 3 System Clock Cycle Time 8 50 8 50 ns t SCLKH System Clock Cycle High Time...

Page 26 - Timing Requirement; Timing Requirements; Switching Characteristic; Applies after V

Rev. C | Page 26 of 48 | December 2006 ADSP-TS201S Table 25. Power-Up Timing 1 Parameter Min Max Unit Timing Requirement t VDD_DRAM V DD_DRAM Stable After V DD , V DD_A , V DD_IO Stable >0 ms 1 For information about power supply sequencing and monitoring solutions, please visit www.analog.com/seq...

Page 27 - Table 27. Normal Reset Timing; RST_IN Deasserted After Strap Pins Stable; Figure 14. Normal Reset Timing; On-chip DRAM Refresh Period; ADSP-TS201 TigerSHARC Processor Programming Reference

ADSP-TS201S Rev. C | Page 27 of 48 | December 2006 Table 27. Normal Reset Timing Parameter Min Max Unit Timing Requirements t RST_IN RST_IN Asserted 2 ms t STRAP RST_IN Deasserted After Strap Pins Stable 1.5 ms Switching Characteristic t RST_OUT RST_OUT Deasserted After RST_IN Deasserted 1.5 ms Figu...

Page 29 - Reset and Booting on Page 9; Figure 15. General AC Parameters Timing; Name

ADSP-TS201S Rev. C | Page 29 of 48 | December 2006 DS2–0 8 Static Pins—Must Be Constant — — — — — — — SCLKRAT2–0 8 Static Pins—Must Be Constant — — — — — — — ENEDREG Static Pins—Must Be Connected to V SS — — — — — — — STRAP SYS 9, 10 Strap Pins 1.5 0.5 — — — — SCLK JTAG SYS 11, 12 JTAG System Pins +...

Page 30 - Table 30. Link Port LVDS Transmit Electrical Characteristics; Figure 16. Link Ports—Transmit Electrical Characteristics

Rev. C | Page 30 of 48 | December 2006 ADSP-TS201S Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing Table 30 and Table 31 with Figure 16 provide the electrical characteristics for the LVDS link ports. The LVDS link port sig-nal definitions represent all differ...

Page 31 - Link Port—Data Out Timing; with; Table 32. Link Port—Data Out Timing; Outputs

ADSP-TS201S Rev. C | Page 31 of 48 | December 2006 Link Port—Data Out Timing Table 32 with Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , and Figure 23 provide the data out timing for the LVDS link ports. Table 32. Link Port—Data Out Timing Parameter Description Min Max Unit Outputs t R...

Page 34 - Link Port—Data In Timing; Table 33. Link Port—Data In Timing; Inputs; Timing is relative to the 0 differential voltage (V; Figure 24. Link Ports—Last Received Quad Word

Rev. C | Page 34 of 48 | December 2006 ADSP-TS201S Link Port—Data In Timing Table 33 with Figure 24 and Figure 25 provide the data in timing for the LVDS link ports. Table 33. Link Port—Data In Timing Parameter Description Min Max Unit Inputs t LCLKIP LxCLKIN Period ( Figure 25 ) Greater of 1.8 or 0...

Page 36 - OUTPUT DRIVE CURRENTS; through; Figure 26. Typical Drive Currents at Strength 0; Figure 28. Typical Drive Currents at Strength 2

Rev. C | Page 36 of 48 | December 2006 ADSP-TS201S OUTPUT DRIVE CURRENTS Figure 26 through Figure 33 show typical I–V characteristics for the output drivers of the ADSP-TS201S processor. The curves in these diagrams represent the current drive capability of the out-put drivers as a function of outpu...

Page 37 - TEST CONDITIONS; Output Disable Time; Figure 31. Typical Drive Currents at Strength 5

ADSP-TS201S Rev. C | Page 37 of 48 | December 2006 TEST CONDITIONS The ac signal specifications (timing parameters) appear in Table 29 on Page 28 . These include output disable time, output enable time, and capacitive loading. The timing specifications for the DSP apply for the voltage reference lev...

Page 38 - Output Enable Time; Capacitive Loading; Output Disable Time on; vs. Load Capacitance at Strength 0; vs. Load Capacitance at Strength 1

Rev. C | Page 38 of 48 | December 2006 ADSP-TS201S Output Enable Time Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driv-ing. The time for the voltage on the bus to ramp by Δ V is dependent on the capacitive load, C L , and t...

Page 39 - vs. Load Capacitance at Strength 7

ADSP-TS201S Rev. C | Page 39 of 48 | December 2006 Figure 41. Typical Output Rise and Fall Time (10% to 90%, V DD_IO = 2.5 V) vs. Load Capacitance at Strength 4 Figure 42. Typical Output Rise and Fall Time (10% to 90%, V DD_IO = 2.5 V) vs. Load Capacitance at Strength 5 Figure 43. Typical Output Ris...

Page 40 - ENVIRONMENTAL CONDITIONS; environmental conditions specified in the; Thermal Characteristics; data sheet specification is not; Parameter; C/W for 0 m/s is for vertically mounted boards. For horizontally

Rev. C | Page 40 of 48 | December 2006 ADSP-TS201S ENVIRONMENTAL CONDITIONS The ADSP-TS201S processor is rated for performance under T CASE environmental conditions specified in the Operating Con- ditions on Page 21 . Thermal Characteristics The ADSP-TS201S processor is packaged in a 25 mm × 25 mm, ...

Page 41 - shows a summary of pin configurations for the; For a more detailed pin summary diagram, see the

ADSP-TS201S Rev. C | Page 41 of 48 | December 2006 576-BALL BGA_ED PIN CONFIGURATIONS Figure 46 shows a summary of pin configurations for the 576-ball BGA_ED package and Table 35 lists the signal-to-ball assignments. Figure 46. 576-Ball BGA_ED Pin Configurations 1 (Top View, Summary) 1 For a more de...

Page 44 - . For more information on SCLK and SCLK_V; on the Analog Devices website (

Rev. C | Page 44 of 48 | December 2006 ADSP-TS201S U1 MSSD0 V1 MSSD2 W1 CONTROLIMP0 Y1 EMU U2 RST_OUT V2 DS2 W2 ENEDREG Y2 TCK U3 ID2 V3 POR_IN W3 TDI Y3 TMR0E U4 DS1 V4 CONTROLIMP1 W4 TDO Y4 FLAG3 U5 V DD_IO V5 V SS W5 V DD_IO Y5 V SS U6 V DD V6 V DD W6 V DD Y6 V DD_IO U7 V DD V7 V DD W7 V DD Y7 V ...

Page 45 - OUTLINE DIMENSIONS; SURFACE MOUNT DESIGN; is provided as an aid to PCB design. For industry-; DETAIL A; Table 36. BGA Data for Use with Surface Mount Design

ADSP-TS201S Rev. C | Page 45 of 48 | December 2006 OUTLINE DIMENSIONS The ADSP-TS201S processor is available in a 25 mm × 25 mm, 576-ball metric thermally enhanced ball grid array (BGA_ED) package with 24 rows of balls (BP-576). SURFACE MOUNT DESIGN Table 36 is provided as an aid to PCB design. For ...

Page 46 - ORDERING GUIDE; Model; Represents case temperature.; Operating Voltage

Rev. C | Page 46 of 48 | December 2006 ADSP-TS201S ORDERING GUIDE Model Temperature Range 1 1 Represents case temperature. InstructionRate 2 2 The instruction rate is the same as the internal processor core clock (CCLK) rate. On-ChipDRAM Operating Voltage Package Option Package Description ADSP-TS20...