Analog Devices ADSP-21020 - Manuals

Analog Devices ADSP-21020 – Manual in PDF format online.

Manuals:

Manual

Manual Analog Devices ADSP-21020

Summary

Page 5 - Figure 2. Basic System Configuration; PIN DESCRIPTIONS; Type

ADSP-21020 REV. C – 5 – 4 1 × CLOCK CLKIN PMA PMD DMACK DMA DMD ADSP-21010 24 48 32 32 2 PMACK 4 DMPAGE PMPAGE FLAG3-0 JTAG 5 4 RCOMP TIMEXP ADDR DATA PROGRAM MEMORY SELECTS OE WE PMS1-0 PMRD PMWR DMRD DMWR DMTS DATA MEMORY ACK PERIPHERALS ADDR DATA ADDR DATA SELECTS SELECTS OE WE OE WE BR BG RESET ...

Page 6 - INSTRUCTION SET SUMMARY

ADSP-21020 REV. C – 6 – PinName Type Function DMPAGE O Data Memory Page Boundary. The ADSP-21020 asserts this pin to signal that a datamemory page boundary has been crossed.Memory pages must be defined in thememory control registers. DMTS I/S Data Memory Three-State Control. DMTS places the data mem...

Page 8 - Table II. Condition and Termination Codes; Name; IMMEDIATE MOVE INSTRUCTIONS; Notation

ADSP-21020 REV. C – 8 – Table II. Condition and Termination Codes Name Description eq ALU equal to zero ne ALU not equal to zero ge ALU greater than or equal to zero lt ALU less than zero le ALU less than or equal to zero gt ALU greater than zero ac ALU carry not ac Not ALU carry av ALU overflow not...

Page 9 - Table III. Universal Registers; Table IV. ALU Compute Operations

ADSP-21020 REV. C – 9 – Table III. Universal Registers Name Function Register FileR15–R0 Register file locations Program SequencerPC* Program counter; address of instruction cur-rently executing PCSTK Top of PC stack PCSTKP PC stack pointer FADDR* Fetch address DADDR* Decode address LADDR Loop termi...

Page 10 - Shifter

ADSP-21020 REV. C – 1 0 – Table V. Multiplier Compute Operations Rn = Rx * Ry ( S S F ) Fn = Fx * Fy MRF = Rx * Ry ( U U I MRB = Rx * Ry ( U U FR Rn = MRF + Rx * Ry ( S S F ) Rn = MRF – Rx * Ry ( S S F ) Rn = MRB + Rx * Ry ( U U I Rn = MRB = Rx * Ry ( U U I MRF = MRF + Rx * Ry ( U U FR MRF = MRF = R...

Page 11 - Function

ADSP-21020 REV. C – 1 1 – Table Vll. Multifunction Compute Operations Fixed-Point Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12Rm=R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 – R15-12MR...

Page 12 - ABSOLUTE MAXIMUM RATINGS*

RECOMMENDED OPERATING CONDITIONS K Grade B Grade T Grade Parameter Min Max Min Max Min Max Unit V DD Supply Voltage 4.50 5.50 4.50 5.50 4.50 5.50 V T AMB Ambient Operating Temperature 0 +70 –40 +85 –55 +125 ° C Refer to Environmental Conditions for information on thermal specifications. ELECTRICAL C...

Page 13 - RESET Width Low; assuming stable V

ADSP-21020 REV. C – 1 3 – TIMING PARAMETERSGeneral Notes See Figure 15 on page 24 for voltage reference levels. Use the exact timing information given. Do not attempt to derive parametersfrom the addition or subtraction of others. While addition or subtraction would yield meaningful results for an i...

Page 14 - Interrupts; IRQ; IRQ; IRQ; Timer

ADSP-21020 REV. C – 1 4 – Interrupts K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement:t SIR IRQ 3-0 Setup before CLKIN High 38 31 25 23 38 + 3DT/4 ns t HIR IRQ 3-0 Hold after CLKIN ...

Page 16 - PMRD

ADSP-21020 REV. C – 1 6 – Bus Request/Bus Grant K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement:t HBR BR Hold after CLKIN High 0 0 0 0 ns t SBR BR Setup before CLKIN High 18 15 13 ...

Page 17 - xTS; Figure 9. External Memory Three-State Control

ADSP-21020 REV. C – 1 7 – External Memory Three-State Control K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement:t STS xTS , Setup before CLKIN High 14 50 12 40 10 33 9 30 14 + DT/4 t...

Page 18 - ns

ADSP-21020 REV. C – 1 8 – Memory Read K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependence* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement:t DAD Address, Select to Data Valid 37 27 20 17 37 + DT ns t DRLD xRD Low to Data Valid 24 18 ...

Page 19 - Figure 10. Memory Read

ADSP-21020 REV. C – 1 9 – CLKIN DATA DMACK, PMACK ADDRESS, SELECT DMPAGE, PMPAGE t DARL t DAP t DAAK t DCKRL t DRAK t SAK t HAK t DAD t DRLD t RWR t HDRH t RW t HDA DMWR, PMWR DMRD, PMRD Figure 10. Memory Read

Page 21 - Figure 11. Memory Write

ADSP-21020 REV. C – 2 1 – CLKIN DATA DMACK, PMACK ADDRESS, SELECT DMPAGE, PMPAGE t DAWL t DAP t DAAK t DCKWL t DWAK t SAK t HAK t WDE t DWHA t WWR t DDWR t DDWH t WW t DAWH t HDWH DMWR, PMWR DMRD, PMRD Figure 11. Memory Write

Page 22 - TRST

ADSP-21020 REV. C – 2 2 – IEEE 1149.1 Test Access Port K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement:t TCK TCK Period 50 40 33 30 t CK ns t STAP TDI, TMS Setup before TCK High 5 ...

Page 24 - Output Enable Time

ADSP-21020 REV. C – 2 4 – TEST CONDITIONSOutput Disable Time Output pins are considered to be disabled when they stopdriving, go into a high-impedance state, and start to decay fromtheir output high or low voltage. The time for the voltage on thebus to decay by ∆ V is dependent on the capacitive loa...

Page 25 - Capacitive Loading

ADSP-21020 REV. C – 2 5 – Capacitive Loading Output delays are based on standard capacitive loads: 100 pFon address, select, page and strobe pins, and 50 pF on all others(see Figure 14). For different loads, these timing parametersshould be derated. See the Hardware Configuration chapter ofthe ADSP-...

Page 26 - ENVIRONMENTAL CONDITIONS; PD; for Various Airflow Values; CPGA with No Heat Sink 12.8; NOTES; is approximately 1; Power Dissipation; Pin; PMS; Power and Ground Guidelines

ADSP-21020 REV. C – 2 6 – ENVIRONMENTAL CONDITIONS The ADSP-21020 is available in a Ceramic Pin Grid Array(CPGA). The package uses a cavity-down configuration whichgives it favorable thermal characteristics. The top surface of thepackage contains a raised copper slug from which much of thedie heat i...

Page 27 - Target System Requirements For Use Of EZ-ICE Emulator

ADSP-21020 REV. C – 2 7 – All GND pins should have a low impedance path to ground. Aground plane is required in ADSP-21020 systems to reduce thisimpedance, minimizing noise. The EVDD and IVDD pins should be bypassed to the groundplane using approximately 14 high-frequency capacitors (0.1 µ F ceramic...

Page 28 - TOP VIEW

ADSP-21020 REV. C – 2 8 – TCK PMA21 PMPAGE TRST RCOMP DMACK TDO DMTS PMWR PMD47 PMD46 PMD44 PMD42 PMD41 PMD38 DMD22 EVDD DMD24 DMD25 DMD26 DMD23 DMD27 DMD28 DMD33 DMD29 DMD35 DMD36 DMD39 DMD34 NC DMS0 DMPAGE DMS2 DMA31 DMA27 DMA26 DMA29 DMA24 DMA19 DMA14 DMA17 PMA0 NC FLAG2 DMA1 DMA3 DMA7 DMA11 PMA2...

Page 29 - BOTTOM VIEW

ADSP-21020 REV. C – 2 9 – DMD7 DMD8 DMA14 DMA13 DMD12 DMD14 DMD18 DMD21 DMD22 DMD26 DMD32 DMD33 DMD37 DMD39 DMA21 DMA17 DMA16 EVDD DMD23 DMD29 DMD34 DMA22 BG BR BOTTOM VIEW (PINS UP) PMD31 PMD35 PMD39 PMD40 PMD44 PMWR PMACK RCOMP PMD27 PMD30 PMD32 PMD37 NC PMD42 PMTS NC NC CLKIN DMACK DMWR PMD11 PMA...

Page 32 - ORDERING GUIDE; Ambient Temperature

ADSP-21020 REV. C – 3 2 – C1601c–5–8/94 PRINTED IN U.S.A. ORDERING GUIDE Ambient Temperature Instruction Cycle Time Part Number* Range Rate (MHz) (ns) Package ADSP-21020KG-80 0 ° C to +70 ° C 20 50 223-Lead Ceramic Pin Grid Array ADSP-21020KG-100 0 ° C to +70 ° C 25 40 223-Lead Ceramic Pin Grid Arra...