Mitel MT90840 - Manual
Mitel MT90840 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Preliminary Information; Figure 2 - Pin Connections
- Page 3 – Pin Description; Name
- Page 5 – TRST
- Page 6 – Functional Description; sec frame. This is also referred to as; Device Operation; Time Slot Interchange Operation (Switching); sec) of data at the input
- Page 7 – Figure 3 - Serial Por t Interface Functional Timing; PCKR; PCKR or PCKT
- Page 8 – Transmit Path
- Page 9 – Serial Data Por t; sec frame, with each individual
- Page 10 – Parallel Data Por t
- Page 11 – Output Driver Enable Control Capability; Timing and Switching Control; sec exists between; Figure 5a - Timing Mode 1 Configuration
- Page 12 – sec) of clock drift and jitter before the buffer
- Page 13 – is not; Figure 6a - Timing Mode 2 Configuration
- Page 14 – PLL; Figure 7 - Timing Mode 3 Configuration
- Page 15 – Figure 8 - Timing Mode 4 Configuration
- Page 16 – Table 1 - MT90840 Throughput Delay Summary
- Page 17 – Balanced Operation (all serial data rates); PPFT
- Page 18 – Serial Data Memory Addressing; Figure 11a - 2.048 Mbps Balanced Mode TPDM
- Page 19 – Addressing
- Page 20 – Microprocessor Por t; Address Mapping of the Internal Registers
- Page 21 – Accessing Internal Memories
- Page 22 – Memory Block-Programming; The SEL2-0 bits in the Control Register are used
- Page 23 – The GPM Register is written. The CPU sets the; Timing Mode Initialization; JTAG Suppor t
- Page 24 – The TAP has the following connections:; Description; EXTEST; Table 3 - Boundary-Scan Instruction Register
- Page 26 – Register Description; ODE
- Page 29 – Internal Memory Description; PPBY
- Page 30 – MC
- Page 31 – Applications; Distributed Isochronous Network; LAN ADAPTER CARD; PSTN
- Page 32 – Absolute Maximum Ratings*; DC Electrical Characteristics
- Page 33 – AC Electrical Characteristics
- Page 34 – Output
- Page 35 – Serial Port with Positive Polarity F0 (GCI)
- Page 36 – tT
- Page 39 – Figure 23 - Per-Channel Tristate Characteristics at all Data Rates
- Page 40 – Figure 24 - Serial Por t Timing for 8.192 Mbps - Timing Modes 2 and 3
- Page 41 – TCP controls the clock-edge
- Page 42 – AC Electrical Characteristics - Parallel Data Port
- Page 43 – Figure 29 - Parallel Por t in Timing Mode 4
- Page 45 – Figure 32 - Intel/National Multiplexed Bus Timing; ALE
- Page 47 – Figure 33 - Motorola Multiplexed Bus Timing; DTA
- Page 49 – Hd
2-231
Features
•
Time slot interchange function between eight
pairs of ST-BUS/GCI/MVIP
streams (512
channels) and parallel data por t
•
Programmable data rates on the parallel por t
(19.44, 16.384, or 6.480 Mbyte/s)
•
Programmable data rates on the serial por t
(2.048 Mbps, 4.096 Mbps or 8.192 Mbps)
•
Suppor ts star and point-to-point connections, and
unidirectional or bidirectional ring topologies for
distributed systems
•
Input-to-output bypass function on the parallel
data por t for use in add/drop applications
•
Provides elastic buffer at parallel input por t in the
receive direction
•
Provides byte switching for up to 2430 channels
•
Per-channel direction control on the serial por t
side
•
Per-channel message mode and high-impedance
control on both parallel and serial por t sides
•
8-bit multiplexed microprocessor por t compatible
with Intel and Motorola microcontrollers
•
Guarantees frame integrity when switching nX64
wideband channels such as ISDN H0 channel
•
Provides exter nal control lines allowing fast
parallel interface to be shared with other devices
•
Diagnostic alar m functions and clock
phase-status word for clock monitoring
•
IEEE 1149 (JTAG) boundar y scan por t
Applications
•
Bridging ST-BUS/MVIP buses to high speed
Time Division Multiplexed backplanes at
SONET rates (STS-1, STS-3)
•
High speed isochronous backbones for
distributed PBX and LAN systems
•
Switch platfor ms of up to 2430 channels with
guaranteed frame integrity for wideband
channels
•
Serial bus control and monitoring
•
Data multiplexing
•
High speed communications interface
ISSUE 2
March 1997
Ordering Information
MT90840AL
100 Pin PQFP
MT90840AP
84 Pin PLCC
-40
°
C to 85
°
C
Figure 1 - Functional Block Diagram
MT90840
Distributed Hyperchannel Switch
Output
Mux &
PDo0
PDo7
2430 Position
TX Path
Connection Memory
Bidirectional
I/O
Driver
8
Serial
to
Parallel
&
Parallel
to
Serial
Conver-
Bidirectional
I/O
Driver
STi7
STi0
STo7
STo0
4
CTo0-3
Timing
Control
Unit
PDi0
PDi7
PCKR
PCKT
RES
PPFRi
PPFTi/o
F0i/o
CPU Interface
Internal
Registers
TEST
Pins
5
8
8
SPCKo
C4/8R1
C4/8R2
IRQ
AD0-7
R/W\WR
AS/ALE
CS
DTA
VDD
VSS
DS/RD
ters
Multiple Pages of 512 Position
TX Path Data Memory
8
512 Position
RX Path
8
Multiple Pages of 2430-Byte
RX Path Data Memory
15
8
8
Connection Memory
JTAG
Drivers
16
Preliminary Information
"Loading the manual" means you need to wait until the file loads and becomes available for online reading. Some manuals are very large, and the time they take to appear depends on your internet speed.
Summary
MT90840 Preliminary Information 2-232 Figure 2 - Pin Connections NC NC NC NC NC 74 56 58 60 62 64 68 70 72 66 12 28 26 24 22 18 16 14 20 32 30 54 10 8 6 4 2 84 82 80 78 76 34 36 38 40 42 44 46 48 50 52 84 PIN PLCC 100 PIN PQFP 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 22 24 26 28 30 32 34 36 3...
Preliminary Information MT90840 2-233 Pin Description Pin # Name Description 84 100 3 43 DS/RD Data Strobe/Read (Input). In Motorola multiplexed-bus mode this pin is DS, anactive high input which works with CS to enable read and write operation. In Intel/National multiplexed-bus mode this pin is RD,...
Preliminary Information MT90840 2-235 59 10 TRST Test Reset (Input). Asynchronously initializes the JTAG TAP controller, placing itin the Test-Logic-Reset state. This pin is pulled high internally when not driven. This pin should be pulsed low on power-up, or held low continuously, to ensurethat the...
