Mitel MT90840 - Manuals - manualsarea.com

Page 2 - Preliminary Information; Figure 2 - Pin Connections

MT90840 Preliminary Information 2-232 Figure 2 - Pin Connections NC NC NC NC NC 74 56 58 60 62 64 68 70 72 66 12 28 26 24 22 18 16 14 20 32 30 54 10 8 6 4 2 84 82 80 78 76 34 36 38 40 42 44 46 48 50 52 84 PIN PLCC 100 PIN PQFP 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 22 24 26 28 30 32 34 36 3...

Page 3 - Pin Description; Name

Preliminary Information MT90840 2-233 Pin Description Pin # Name Description 84 100 3 43 DS/RD Data Strobe/Read (Input). In Motorola multiplexed-bus mode this pin is DS, anactive high input which works with CS to enable read and write operation. In Intel/National multiplexed-bus mode this pin is RD,...

Page 5 - TRST

Preliminary Information MT90840 2-235 59 10 TRST Test Reset (Input). Asynchronously initializes the JTAG TAP controller, placing itin the Test-Logic-Reset state. This pin is pulled high internally when not driven. This pin should be pulsed low on power-up, or held low continuously, to ensurethat the...

Page 6 - Functional Description; sec frame. This is also referred to as; Device Operation; Time Slot Interchange Operation (Switching); sec) of data at the input

MT90840 Preliminary Information 2-236 Functional Description The MT90840 Distributed Hyperchannel Switch is alarge switching, multiplexing, and rate-adaptingdevice. The MT90840 bridges serial-bus telecomcomponents, using the Mitel ST-BUS or otherindustry-standard serial buses, onto a higher speed“ba...

Page 7 - Figure 3 - Serial Por t Interface Functional Timing; PCKR; PCKR or PCKT

Preliminary Information MT90840 2-237 Figure 3 - Serial Por t Interface Functional Timing Figure 4 - Parallel Data Por t Functional Timing C4/8R1&2 Serial I/O2 Mbps Serial I/O4 Mbps Frame Boundary Established by F0 Ch. 31 Bit 1 Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 63 Bit 2 Ch. 63 Bit 1 Ch. 6...

Page 8 - Transmit Path

MT90840 Preliminary Information 2-238 an address-value in the path’s Data Memory. A givenoutput time slot is controlled by programming theConnection Memory control-address with theaddress-value of the source input time slot. At thesame control-address the output time slot is enabledor tri-stated and...

Page 9 - Serial Data Por t; sec frame, with each individual

Preliminary Information MT90840 2-239 programmed to switch parallel inputs to paralleloutputs. For each parallel output channelcontrol-address, the Tx Path Connection Memory isprogrammed with the 12-bit address-value of thedesired parallel input channel. Serial Data Por t The serial por t consists o...

Page 10 - Parallel Data Por t

MT90840 Preliminary Information 2-240 Register enables the internal divider, and the SPCKooutput (and internal 4.096 MHz clocks) are driven bythe clock divided-down from PCKR. At 16.384 MHz,this is a simple divide-by-4, and the SPCKo outputjitter will depend on the PCKR input jitter. At 19.44MHz, th...

Page 11 - Output Driver Enable Control Capability; Timing and Switching Control; sec exists between; Figure 5a - Timing Mode 1 Configuration

Preliminary Information MT90840 2-241 streams, and trigger the PPCE interrupt bit. PPCEwill be triggered by PPFRi moving from the expectedtime, but PPCE will not be triggered by a missingPPFRi. If the PPFRi input is held asser ted, theparallel I/O will “lock up” and operation will bedisrupted (inclu...

Page 12 - sec) of clock drift and jitter before the buffer

MT90840 Preliminary Information 2-242 TM1. This allows for flexible round-trip data delays instar or ring type networks. An elastic buffer on thereceive parallel por t compensates for the differencein phase between PPFRi/PCKR and F0i/C4. Theelastic buffer can also tolerate up to 50 µ sec +/- 25 µ se...

Page 13 - is not; Figure 6a - Timing Mode 2 Configuration

Preliminary Information MT90840 2-243 The transmit path does not provide an elastic buffer,and therefore the serial por t clock must be tightlylocked (in frequency) to the parallel por t clock(PCKR). (Jitter less than +/- 100nsec.) This may beachieved in one of two ways: use of the internal clockdiv...

Page 14 - PLL; Figure 7 - Timing Mode 3 Configuration

MT90840 Preliminary Information 2-244 Timing Mode 3 (TM3) - Bus Slave Synchronous Parallel Por t With ST-BUS ClockSlave Timing Mode 3 is used where the main TDM clock ref-erence resides on the parallel port side of the system,and where the receive parallel port and the transmitparallel port are alig...

Page 15 - Figure 8 - Timing Mode 4 Configuration

Preliminary Information MT90840 2-245 Timing Mode 4 (TM4) - Parallel Data Switching Timing Mode 4 is used to provide switching of up to2430 parallel input channels to the same number ofparallel output channels. Parallel TDM data isclocked in at PDi0-7 by PCKR, framed by PPFRi.Switching is performed ...

Page 16 - Table 1 - MT90840 Throughput Delay Summary

MT90840 Preliminary Information 2-246 Table 1 - MT90840 Throughput Delay Summary Naming rules:ELD: ELastic Delay, measured from PPFRi to F0i (4.4 to 129.4 µ sec). P/S:Parallel-to-Serial data path.Pi:Parallel Input channel time, expressed in delay after PPFRi (0 to 125 µ sec). Po:Parallel Output chan...

Page 17 - Balanced Operation (all serial data rates); PPFT

Preliminary Information MT90840 2-247 TPCM High location is output on the correspondingCTo pin once every frame. See Figure 9. The controloutputs can be used to control other devices, suchas buffers, to allow sharing of the parallel por t databus. Per-channel Tri-state (Serial and Parallel)The MT908...

Page 18 - Serial Data Memory Addressing; Figure 11a - 2.048 Mbps Balanced Mode TPDM

MT90840 Preliminary Information 2-248 all 16 serial streams can be individually controlled,so that up to 512 channels can be either transmittedor received. As an example, if all DC bit locations ofRPCM High are set HIGH, all 512 channels onSTo0-7 and STi0-7 will be configured as outputs. Ifall DC bi...

Page 19 - Addressing

Preliminary Information MT90840 2-249 Figure 12a - 2.048 Mbps Add/Drop Mode TPDM Addressing Figure 12b - 2.048 Mbps Add/Drop Mode RPCM Addressing 4.096 Mbps ModeThe 4.096 Mbps mode has 8 input and 8 outputstreams, and 64 channels per stream. Therefore 3bits are used to address the 8 streams, and 6 b...

Page 20 - Microprocessor Por t; Address Mapping of the Internal Registers

MT90840 Preliminary Information 2-250 Figure 14a - 8.192 Mbps TPDM Addressing Figure 14b - 8.196 Mbps RPCM Addressing Microprocessor Por t An 8-bit multiplexed parallel microprocessor por t isprovided on the MT90840 to allow an attached CPUto configure and read internal registers andmemories. The MT...

Page 21 - Accessing Internal Memories

Preliminary Information MT90840 2-251 shor t, or a signal contention, prevents the DTA pinfrom reaching a valid logic HIGH, it will continue todrive for approximately 15 nsec before switching tohigh-impedance. Accessing Internal Memories The Data and Connection memories of the MT90840are connected t...

Page 22 - Memory Block-Programming; The SEL2-0 bits in the Control Register are used

MT90840 Preliminary Information 2-252 the DTA pin will be asser ted (as the data is stored inthe write-pipeline) but the next CPU access will notsee DTA asser ted. No clocks are necessary forregister accesses (but if the write-pipeline is hung,the registers cannot be accessed). If the MT90840 ishung...

Page 23 - The GPM Register is written. The CPU sets the; Timing Mode Initialization; JTAG Suppor t

Preliminary Information MT90840 2-253 DR1-0 and FDC in the IMS register) beforeprogramming the RPCM. b) The GPM Register is written. The CPU sets the Block-Programming Enable (BPE) bit to HIGHand the Block-Programming Data (BPD7-4) bitsto the desired value. This action causes thecontents of the BPD7...

Page 24 - The TAP has the following connections:; Description; EXTEST; Table 3 - Boundary-Scan Instruction Register

MT90840 Preliminary Information 2-254 I/O pin of the IC. The operation of the boundary-scancircuitry is controlled by a Test Access Por t (TAP)Controller. Test Access Por t (TAP)The Test Access Por t (TAP) has five signals andprovides access to the test logic defined by the JTAGstandard. The TAP has...

Page 26 - Register Description; ODE

MT90840 Preliminary Information 2-256 Register Description Interface Mode Selection Register (IMS) - READ/WRITE 7 6 5 4 3 2 1 0 DR1 DR0 PPS1 PPS0 ODE 0 0 FDC DR1-0 Serial Por t Data Rate Selection. Select one of three different data rates at the serial inputs and outputs of theMT90840. DR1 DR0 Data ...

Page 29 - Internal Memory Description; PPBY

Preliminary Information MT90840 2-259 Internal Memory Description OE/CTo0 Output Enable. Provides per channel tr istate control on the parallel por t side. It controls the MT90840 parallel output drivers to disable (tristate, when LOW) or enable (when HIGH) the transmission of data from the device. ...

Page 30 - MC

MT90840 Preliminary Information 2-260 MC Message Channel: The message channel contents are provided by the CPU in bits AB0-7 in the Rx Path ConnectionMemor y Low. If MC is HIGH, the contents of the corresponding location of RPCM Low are output on this serial por tchannel. If MC is LOW, the contents ...

Page 31 - Applications; Distributed Isochronous Network; LAN ADAPTER CARD; PSTN

Preliminary Information MT90840 2-261 Applications Distributed Isochronous Network Low latency isochronous backbones provide for thedeployment of systems that require cost effectiveimplementation, high bandwidth, predictable datatransfer delays and direct synchronization with thewide area network. S...

Page 32 - Absolute Maximum Ratings*; DC Electrical Characteristics

MT90840 Preliminary Information 2-262 synchronization scheme may be used in applicationssuch as the proposed MVIP multi-chassis level 3interface (MC-3 system) utilizing point-to-point orpoint-to-multipoint switching connections. When the MT90840 operates in a ring application,the Parallel Data Bypas...

Page 33 - AC Electrical Characteristics

Preliminary Information MT90840 2-263 AC Electrical Characteristics - Voltages are with respect to ground (V SS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 C4/8 Input - Clock Period:4.096 MHz (2.048 & 4.096 Mbps)8.192 MHz (8.192 Mbps) SPCKo Output - Clock...

Page 34 - Output

MT90840 Preliminary Information 2-264 ‡ Typical figures are at 25 ° C and are for design aid only: not guaranteed and not subject to production testing. Figure 17 - Output Test Load 10 STo Delay from High-Z to Active 2.048 and 4.096 Mbps (TM2 &TM3)2.048 and 4.096 Mbps (TM1)8.192 Mbps (STio0-3) t...

Page 35 - Serial Port with Positive Polarity F0 (GCI)

Preliminary Information MT90840 2-265 Figure 18 - Serial Por t Timing for 2.048 Mbps Operation - TM2 (SFDi = 1) and TM1 C4/8R1 t frw STi0-7 STo0-7 (4.096 MHz) bit 7, ch. 0 bit 0, ch. 31 bit 7, ch. 0 bit 0, ch. 31 t stih t stis t clkh Serial Port with Negative Polarity F0 (ST-BUS) t sod t frh t frs t...

Page 36 - tT

MT90840 Preliminary Information 2-266 Figure 19 - Serial Por t Timing for 2.048 Mbps - TM2 (SFDi = 0) and TM3 t sod STo0-7 SPCKo (4.096 MHz) STi0-7 t stis t stih F0o output bit 7, ch. 0 bit 6, ch. 0 bit 7, ch.0 bit 0, ch.31 bit 0, ch. 31 Serial Port with Positive Polarity F0 (GCI) t df (8 kHz) t df ...

Page 39 - Figure 23 - Per-Channel Tristate Characteristics at all Data Rates

Preliminary Information MT90840 2-269 Figure 22 - Serial Por t Timing for 8.192 Mbps - TM1 and TM2 (SFDi = 1) Figure 23 - Per-Channel Tristate Characteristics at all Data Rates STo0-7 C4/8R1(8.192 MHz) STi0-7 F0i input bit 0, ch.127 bit 7, ch. 0 bit 6, ch. 0 bit 7 (8 kHz) Note: Polarity of F0i is au...

Page 40 - Figure 24 - Serial Por t Timing for 8.192 Mbps - Timing Modes 2 and 3

MT90840 Preliminary Information 2-270 Figure 24 - Serial Por t Timing for 8.192 Mbps - Timing Modes 2 and 3 STo0-7 C4/8R1**(8.192 MHz STi0-7 F0o output bit 0, ch.127 bit 7, ch. 0 bit 6, ch. 0 bit 7 (8 kHz) Frame Sync with Positive Polarity (SPFP = 1) t stis t stih t df t df t sod t t t clkh t clk t ...

Page 41 - TCP controls the clock-edge

Preliminary Information MT90840 2-271 Figure 25 - Timing for the Parallel Por t External Control Lines CTo0-3 Figure 26 - TM1 Parallel Por t Transmit Timing (TM1 & PFDI = 1, PPFT is an input) Figure 27 - Parallel Por t Transmit Timing (PFDI = 0, PPFT is an output) PDo0-7 CTo0-3 PCKT/PCKR TCP con...

Page 42 - AC Electrical Characteristics - Parallel Data Port

MT90840 Preliminary Information 2-272 Figure 28 - Parallel Por t Receive Timing ‡ Typical figures are at 25 ° C and are for design aid only: not guaranteed and not subject to production testing. AC Electrical Characteristics - Parallel Data Port Characteristics Sym Min Typ ‡ Max Units Test Condition...

Page 43 - Figure 29 - Parallel Por t in Timing Mode 4

Preliminary Information MT90840 2-273 Figure 29 - Parallel Por t in Timing Mode 4 Figure 30 - Phase Variation Between C4/8R1 & C4/8R2 and PCKT Inputs for TM1 Operation Figure 31 - Phase Variation Between C4 and PCKR Inputs for TM2 Operation PPFRi PPFT PCKR TCP = 0 PPFT TCP = 1 Note: For the PPFT...

Page 45 - Figure 32 - Intel/National Multiplexed Bus Timing; ALE

Preliminary Information MT90840 2-275 Figure 32 - Intel/National Multiplexed Bus Timing ALE AD0-AD7 CS RD WR DTA t alw t ads t adh DATA ADDRESS t alrd t csrw t dhr t dhw t csw t alwr t akd t ddr t akh 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V t dsw t csr t rst t rdd

Page 47 - Figure 33 - Motorola Multiplexed Bus Timing; DTA

Preliminary Information MT90840 2-277 Figure 33 - Motorola Multiplexed Bus Timing CS DTA AD0-13RD DS R/W AS ADDRESS ADDRESS DATA DATA t rwh t rws t asw t dsh t ads t adh t dhw t dhr t css t csh t akd t akh t ddr 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V AD0-7WR t dss

Page 49 - Hd

Preliminary Information MT90840 2-279 Figure 36 - 84 PLCC Mechanical Drawing Figure 37 - 100 Pin PQF Mechanical Drawing F D 1 D H E 1 I A 1 A G D 2 E E 2 Dim Min Max A 0.165 (4.20) 0.200 (5.08) A 1 0.090 (2.29) 0.130 (3.30) D/E 0.185 (30.10) 1.195 (30.35) D 1 /E 1 1.150 (29.210) 1.158 (29.413) D 2 /...