Xilinx XAPP721 - Manuals - manualsarea.com

Page 2 - Write Datapath; Figure 3; Command and Control Timing

Write Datapath R Write Datapath The write datapath uses the built-in OSERDES available in every Virtex-4 I/O. The OSERDES transmits the data (DQ) and strobe (DQS) signals. The memory specification requires DQS tobe transmitted center-aligned with DQ. The strobe (DQS) forwarded to the memory is 180 d...

Page 3 - Command WRITE

Write Datapath R Figure 3: Write Data Transmitted Using OSERDES Figure 4: Write Strobe (DQS) and Data (DQ) Timing for a Write Latency of Four D1 D2 D3 D4 CLKDIV CLK CLKdiv_90 CLKfast_90 OSERDES DQ IOB ChipSync TM Circuit Write Data Words 0-3 X721_03_080305 CLKfast_0 Clock Forwarded to Memory Device ...

Page 4 - Write Timing Analysis; Table 1

Write Datapath R Write Timing Analysis Table 1 shows the write timing analysis for an interface at 333 MHz (667 Mb/s). Table 1: Write Timing Analysis at 333 MHz Uncertainty Parameters Value Uncertainties before DQS Uncertainties after DQS Meaning T CLOCK 3000 Clock period. T MEMORY_DLL_DUTY_CYCLE_DI...

Page 5 - Controller to Write Datapath Interface; Table 2

Write Datapath R Controller to Write Datapath Interface Table 2 lists the signals required from the controller to the write datapath. Table 2: Controller to Write Datapath Signals Signal Name Signal Width Signal Description Notes ctrl_WrEn 1 Output from the controller to the write datapath. Write DQ...

Page 7 - Read Datapath; Figure 7; Read Timing Analysis; Read Data Capture Using ISERDES; IOB; DQ

Read Datapath R Read Datapath The read datapath comprises the read data capture and recapture stages. Both stages are implemented in the built-in ISERDES available in every Virtex-4 I/O. The ISERDES has three clock inputs: CLK, OCLK, and CLKDIV. The read data is captured in the CLK (DQS) domain, rec...

Page 8 - Table 3; Per Bit Deskew Data Capture Technique; Read Timing Analysis at 333 MHz

Read Datapath R Table 3 shows the read timing analysis at 333 MHz required to determine the delay required on DQ bits for centering DQS in the data valid window. Per Bit Deskew Data Capture Technique To ensure reliable data capture in the OCLK and CLKDIV domains in the ISERDES, a trainingsequence is...

Page 9 - Figure 8; Read Data and Strobe Delay

Read Datapath R Figure 8 shows the timing waveform for read data and strobe delay determination. The waveforms on the left show a case where the DQS is delayed due to BUFIO and clockingresource, and the ISERDES outputs do not match the expected data pattern. The waveforms on the right show a case wh...

Page 10 - Controller to Read Datapath Interface; Table 4

Read Datapath R Controller to Read Datapath Interface Table 4 lists the control signals between the controller and the read datapath. Table 4: Signals between Controller and Read Datapath Signal Name Signal Width Signal Description Notes ctrl_Dummyread_Start 1 Output from the controller to the read ...

Page 11 - Reference Design; shows the read-enable logic; Reference Design Hierarchy

Reference Design R The ctrl_RdEn signal is required to validate read data because the DDR2 SDRAM devices donot provide a read valid or read-enable signal along with read data. The controller generates this read-enable signal based on the CAS latency and the burst length. This read-enable signal is i...