Page 3 - Revision History
UG518 (v1.1) August 19, 2009 www.xilinx.com SP601 Hardware User Guide Revision History The following table shows the revision history for this document. Date Version Revision 07/15/2009 1.0 Initial Xilinx release. 08/19/2009 1.1 • Added Appendix C, “VITA 57.1 FMC Connections.” • Updated Figure 1-18 ...
Page 5 - Preface: About This Guide; Table of Contents
SP601 Hardware User Guide www.xilinx.com 5 UG518 (v1.1) August 19, 2009 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Resources . . . . . . . . . . . . . . . . . . . . ...
Page 6 - Appendix A: References
6 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Appendix A: References Appendix B: Default Jumper and Switch Settings Appendix C: VITA 57.1 FMC Connections Appendix D: SP601 Master UCF
Page 7 - Preface; About This Guide; Guide Contents; Additional Resources; Typographical
SP601 Hardware User Guide www.xilinx.com 7 UG518 (v1.1) August 19, 2009 Preface About This Guide This manual accompanies the Spartan®-6 FPGA SP601 Evaluation Board and contains information about the SP601 hardware and software tools. Guide Contents This manual contains the following chapters: • Chap...
Page 8 - Online Document
8 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Preface: About This Guide Online Document The following conventions are used in this document: Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the...
Page 9 - Chapter 1; SP601 Evaluation Board; Overview; Additional Information
SP601 Hardware User Guide www.xilinx.com 9 UG518 (v1.1) August 19, 2009 Chapter 1 SP601 Evaluation Board Overview The SP601 board enables hardware and software developers to create or evaluate designs targeting the Spartan®-6 XC6SLX16-2CSG324 FPGA. The SP601 provides board features for evaluating th...
Page 10 - Features
10 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board Features The SP601 board provides the following features: • 1. Spartan-6 XC6SLX16-2CSG324 FPGA • 2. 128 MB DDR2 Component Memory • 3. SPI x4 Flash • 4. Linear Flash BPI • 5. 10/100/1000 Tri-Spe...
Page 11 - Block Diagram; Related Xilinx Documents; SP601 Features and Banking
SP601 Hardware User Guide www.xilinx.com 11 UG518 (v1.1) August 19, 2009 Related Xilinx Documents Block Diagram Figure 1-1 shows a high-level block diagram of the SP601 and its peripherals. Related Xilinx Documents Prior to using the SP601 Evaluation Board, users should be familiar with Xilinx resou...
Page 12 - Detailed Description
12 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board Detailed Description Figure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document. The numbered features in Figure 1-2 correlate to...
Page 13 - I/O Voltage Rail of FPGA Banks
SP601 Hardware User Guide www.xilinx.com 13 UG518 (v1.1) August 19, 2009 Detailed Description 1. Spartan-6 XC6SLX16-2CSG 3 24 FPGA A Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is installed on the Embedded Development Board. Configuration The SP601 supports configuration in the following modes: • Master ...
Page 14 - References; FPGA On-Chip (OCT) Termination External Resistor Requirements
14 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board References See the Xilinx Spartan-6 FPGA documentation for more information at http://www.xilinx.com/support/documentation/spartan-6.htm . 2. 128 MB DDR2 Component Memory There are 128 MB of DD...
Page 17 - UCF Location Constraints for DDR2 SDRAM Data I/O Pins
SP601 Hardware User Guide www.xilinx.com 17 UG518 (v1.1) August 19, 2009 Detailed Description Figure 1-4 provides the UCF constraints for the DDR2 SDRAM data pins, including the I/O pin assignment and I/O standard used. Figure 1-5 provides the UCF constraints for the DDR2 SDRAM control pins, includi...
Page 18 - J12 SPI Flash Programming Header
18 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board 3 . SPI x4 Flash The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are 3....
Page 20 - UCF Location Constraints for BPI Flash Connections
20 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board Figure 1-8 provides the UCF constraints for the SPI serial flash PROM. References See the Winbond Serial Flash specifications for more information at http://www.winbond- usa.com/hq/enu/ProductA...
Page 23 - PHY Configuration Pins; PHY Connections
SP601 Hardware User Guide www.xilinx.com 23 UG518 (v1.1) August 19, 2009 Detailed Description 5. 10/100/1000 Tri-Speed Ethernet PHY The SP601 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports a GMII/MII interface from the FP...
Page 25 - USB Type B Pin Assignments and Signal Definitions; UCF Location Constraints for CP2103GM Connections
SP601 Hardware User Guide www.xilinx.com 25 UG518 (v1.1) August 19, 2009 Detailed Description References See the Marvell Alaska Gigabit Ethernet Transceiver product page for more information at http://www.marvell.com/products/transceivers/alaska_gigabit/index.jsp . Also, see the Xilinx Tri-Mode Ethe...
Page 26 - IIC Bus Topology
26 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board References Technical information on the Silicon Labs CP2103GM and the VCP drivers can be found on their website at https://www.silabs.com/Pages/default.aspx . In addition, see some of the Xilin...
Page 27 - IIC Memory Connections
SP601 Hardware User Guide www.xilinx.com 27 UG518 (v1.1) August 19, 2009 Detailed Description 8-Kb NV Memory The SP601 hosts a 8-Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage memory device (U7). The IIC address of U7 is 0b1010100, and U7 is not write protected (WP pin 7 is tied to GND)....
Page 28 - UCF Location Constraints for Oscillator Socket Connections
28 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board Oscillator Socket (Single-Ended, 2.5V or 3 . 3 V) One populated single-ended clock socket (X2) is provided for user applications. The option of 3.3V or 2.5V power may be selected via a 0 ohm re...
Page 32 - Status LEDs
32 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board 10. Status LEDs Table 1-14 defines the status LEDs. Table 1-14: Status LEDs Reference Designator Signal Name Color Label Description DS1 FMC_PWR_GOOD_ FLASH_RST_B Green PWR GOOD Indicates power...
Page 33 - FPGA Awake LED and Suspend Jumper; Sus; UCF Location Constraints for FPGA Awake/Suspend Mode Jumper
SP601 Hardware User Guide www.xilinx.com 33 UG518 (v1.1) August 19, 2009 Detailed Description 11. FPGA Awake LED and Suspend Jumper The suspend mode jumper permits the FPGA to enter an inactive, "suspend" mode. The FPGA Awake LED DS8 will go out when the FPGA enters this mode. See the Sparta...
Page 34 - FPGA INIT and DONE LEDs; FPGA INIT and DONE LED Connections; UCF Location Constraints for FPGA INIT and DONE
34 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board 12. FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and configuration status LEDs are present on the SP601. The INIT LED DS10 comes on after the FPGA powers up and completes its intern...
Page 35 - User LEDs; GPIO LED 3
SP601 Hardware User Guide www.xilinx.com 35 UG518 (v1.1) August 19, 2009 Detailed Description 1 3 . User I/O The SP601 provides the following user and general purpose I/O capabilities: • User LEDs • User DIP switch • Pushbutton switches • CPU Reset pushbutton switch • GPIO male pin header Note: All ...
Page 36 - User DIP switch
36 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board User DIP switch The SP601 includes an active high four pole DIP switch, as described in Figure 1-24 and Table 1-18 . DS13 GPIO_LED_2 Green C4 DS14 GPIO_LED_3 Green A4 Table 1-17: User LEDs (Con...
Page 37 - User Pushbutton Switches; Pushbutton Switch Connections; us
SP601 Hardware User Guide www.xilinx.com 37 UG518 (v1.1) August 19, 2009 Detailed Description User Pushbutton Switches The SP601 provides five active high pushbutton switches: SW6, SW4, SW5, SW7 and SW9. The five pushbuttons all have the same topology as the sample shown in Figure 1-25 . Four pushbu...
Page 38 - GPIO Male Pin Header; GPIO Male Pin Header Topology
38 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board GPIO Male Pin Header The SP601 provides a 2X6 GPIO male pin header supporting 3.3V power, GND and eight I/Os. Figure 1-26 and Table 1-20 describe the J13 GPIO Male Pin Header. X-Ref Target - Fi...
Page 40 - Power Management; AC Adapter and 5V Input Power Jack/Switch; Onboard Power Supplies; FPGA_PROG_B Pushbutton Switch Connections
40 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board 14. FPGA_PROG_B Pushbutton Switch The SP601 provides one dedicated, active low FPGA_PROG_B pushbutton switch, as shown in Figure 1-28 . Power Management AC Adapter and 5V Input Power Jack/Switc...
Page 41 - Power Supply
SP601 Hardware User Guide www.xilinx.com 41 UG518 (v1.1) August 19, 2009 Power Management The SP601 uses power solutions from LTC. An estimate of the current draw on the various power supply rails is shown in Table 1-22 . X-Ref Target - Figure 1- 3 0 Figure 1-30: Power Supply 5V PWR J a ck D ua l S ...
Page 42 - Configuration Options; JTAG Configuration; JTAG Chain
42 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 Chapter 1: SP601 Evaluation Board Configuration Options The FPGA on the SP601 Evaluation Board can be configured by the following methods: • “3. SPI x4 Flash,” page 18 • “4. Linear Flash BPI,” page 20 • “JTAG Configuration,” pa...
Page 45 - Appendix A
SP601 Hardware User Guide www.xilinx.com 45 UG518 (v1.1) August 19, 2009 Appendix A References This section provides references to documentation supporting Spartan-6 FPGAs, tools, and IP. For additional information, see www.xilinx.com/support/documentation/index.htm . Documents supporting the SP601 ...
Page 47 - Appendix B; Default Jumper and Switch Settings
SP601 Hardware User Guide www.xilinx.com 47 UG518 (v1.1) August 19, 2009 Appendix B Default Jumper and Switch Settings Table B-1 shows the default jumper and switch settings for the SP601. Table B-1: Default Jumper and Switch Settings REFDES Type/Function Default SW1 SLIDE, POWER ON-OFF OFF SW2 DIP,...
Page 49 - Appendix C; VITA 57.1 FMC Connections; VITA 57.1 FMC LPC Connections
SP601 Hardware User Guide www.xilinx.com 49 UG518 (v1.1) August 19, 2009 Appendix C VITA 57.1 FMC Connections Table C-1 shows the VITA 57.1 FMC LPC connections. Table C-1: VITA 57.1 FMC LPC Connections J1 FMC LPC Pin Schematic Netname U1 FPGA Pin J1 FMC LPC Pin Schematic Netname U1 FPGA Pin C10 FMC_...
Page 51 - Appendix D
SP601 Hardware User Guide www.xilinx.com 51 UG518 (v1.1) August 19, 2009 Appendix D SP601 Master UCF The UCF template is provided for designs that target the SP601. Net names provided in the constraints below correlate with net names on the SP601 rev. C schematic. On identifying the appropriate pins...
