Xilinx UG154 - Manual

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com UG154 March 24, 2008 Chapter 4: Detailed Example Design Table 4-1: Project Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 4-2: Component Name Directory . . . . . . . . . . ...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 11 UG154 March 24, 2008 R Preface About This Guide This guide provides information about generating the Xilinx LogiCORE™ IP SPI-4.2 core, customizing and simulating the core using the provided example design, and running the design files through impl...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 13 UG154 March 24, 2008 R Chapter 1 Introduction The LogiCORE IP SPI-4.2 (PL4) core is a fully verified design solution that supports Verilog and VHDL. The example design in this guide is provided in both Verilog and VHDL. This chapter introduces the...

14 www.xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 1: Introduction R Contact your local Xilinx representative for a closer review and estimate of the effort required to meet your specific design requirements. Additional Core Resources For detailed information and updat...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 15 UG154 March 24, 2008 R Chapter 2 Licensing the Core This chapter provides instructions for obtaining a license for the core so that you can use the core in a design. The SPI-4.2 core is provided under the terms of the Xilinx LogiCORE Site License ...

16 www.xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 2: Licensing the Core R be tested in the target device for a limited time before timing out . The core can be reactivated by reconfiguring the device after a time out. You can obtain the Full System Evaluation License ...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 17 UG154 March 24, 2008 Installing Your License File R Follow the instructions in the lounge to fill out the license request form; then click Submit to automatically generate the license. An email containing the license and installation instructions ...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 19 UG154 March 24, 2008 R Chapter 3 Quick Start Example Design The quick start steps provide information to quickly generate a SPI-4.2 core, run the design through implementation with the Xilinx tools, and simulate the example design using the provid...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 21 UG154 March 24, 2008 Implementing the Example Design R Implementing the Example Design After generating a core with a Full System Hardware Evaluation or Full license, the netlists and the example design can be processed by the Xilinx implementatio...

22 www.xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 3: Quick Start Example Design R To run a VHDL or Verilog functional simulation of the example design using NCSIM: 1. Set the current directory to: <quickstart> /simulation/functional/ 2. Execute the simulation sc...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 25 UG154 March 24, 2008 R Chapter 4 Detailed Example Design This chapter provides detailed information about the example design, including a description of files and the directory structure generated by the Xilinx CORE Generator, the purpose and cont...

26 www.xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Example Design R Directory and File Contents The SPI-4.2 core directories and their associated files are defined in the following sections. <project directory> The project directory contains all the C...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 31 UG154 March 24, 2008 Implementation and Simulation Scripts R simulation/timing The timing directory contains timing simulation scripts provided with the core. Implementation and Simulation Scripts The implementation script is either a shell script...

32 www.xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Example Design R If the core was generated with the Full System Hardware Evaluation or the Full license, the implementation script is present and performs the following steps: 1. Synthesizes the example des...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 33 UG154 March 24, 2008 Example Design Configuration R connects to a SPI-4.2 PHY layer device or network processor. Figure 4-1 shows the example design modules architecture and interfaces to the SPI-4.2 core. Loopback Module The Loopback Module conne...

34 www.xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Example Design R Demonstration Test Bench The demonstration test bench emulates a PHY device by generating and receiving packet data across the SPI-4.2 interface. The interface between the demonstration tes...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 35 UG154 March 24, 2008 Demonstration Test Bench R • Status Monitor • Testcase Clock Generator The Clock Generator creates all of the clocks that are used in the Design Example, including SysClk , RDClk2x , UserClk , TSClk , and SnkIdelayRefClk . The...

36 www.xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Example Design R Startup Module The Startup Module contains three functions: DCM setup, calendar loading, and Dynamic Phase Alignment (DPA) Initialization. These functions are described in detail in the fol...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 37 UG154 March 24, 2008 Demonstration Test Bench R • RDCLK_RST Holds DCMReset_RDClk for 8 cycles then releases it • RDCLK_LCK Waits for the Locked_RDClk signal. • TSCLK_RST Holds DCMReset_TSClk for 12 cycles then releases it. • TSCLK_LCK Waits for th...

38 www.xilinx.com SPI-4.2 v8.5 Getting Started Guide UG154 March 24, 2008 Chapter 4: Detailed Example Design R Procedures Module The procedures module is a package of functions instantiated in the testcase module to simplify sending data and status to the stimulus module. Using these functions, you ...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 39 UG154 March 24, 2008 Demonstration Test Bench R Lastly, the signal SnkInFrame is created in the status monitor by inverting SnkOof . This signal is used by the stimulus module to send training. See Appendix C, “Data and Status Monitor Warnings.” C...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 41 UG154 March 24, 2008 Demonstration Test Bench R Testcase Module The testcase module generates data and sends it to the stimulus module, which in turn transmits data to the Sink core and status to the Source core. The following data is created in t...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 43 UG154 March 24, 2008 Demonstration Test Bench R and the status for that channel. This sends the status and the channel to the stimulus module for transmission to the core. The stimulus module ensures that the status is sent in the correct location...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 45 UG154 March 24, 2008 R Appendix A VHDL Details Procedures Module The procedures module is a package of functions instantiated in the testcase module to simplify the sending of data and status to the Stimulus module. By using these functions, the u...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 49 UG154 March 24, 2008 R Appendix B Verilog Details Procedures Module The procedures module is a package of functions instantiated in the Testcase module to simplify sending data and status to the Stimulus module. Use these functions to create any d...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 51 UG154 March 24, 2008 Random Testcase Sample Code R The send_status procedure is used to change the status for a particular channel. The get_status procedure is called to check status of a specific channel. It will cause the status value of that ch...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 55 UG154 March 24, 2008 R Appendix C Data and Status Monitor Warnings The Data and Status monitors continuously check data sent to and received from the demonstration test bench. There are several common warnings that occur when the Testcase module i...

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 57 UG154 March 24, 2008 R Appendix D Timing Simulation Warning and Error Messages There are several common simulation warnings and error messages when timing simulation is run on the example design. These warnings and messages are described in this a...