Xilinx XAPP721 - Manual
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Table of Contents:
- Page 2 – Write Datapath; Figure 3; Command and Control Timing
- Page 3 – Command WRITE
- Page 4 – Write Timing Analysis; Table 1
- Page 5 – Controller to Write Datapath Interface; Table 2
- Page 7 – Read Datapath; Figure 7; Read Timing Analysis; Read Data Capture Using ISERDES; IOB; DQ
- Page 8 – Table 3; Per Bit Deskew Data Capture Technique; Read Timing Analysis at 333 MHz
- Page 9 – Figure 8; Read Data and Strobe Delay
- Page 10 – Controller to Read Datapath Interface; Table 4
- Page 11 – Reference Design; shows the read-enable logic; Reference Design Hierarchy
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Summary
This application note describes a data capture technique for a high-performance DDR2
SDRAM interface. This technique uses the Input Serializer/Deserializer (ISERDES) and Output
Serializer/Deserializer (OSERDES) features available in every Virtex™-4 I/O. This technique
can be used for memory interfaces with frequencies of 267 MHz (533 Mb/s) and above.
Introduction
A DDR2 SDRAM interface is source-synchronous where the read data and read strobe are
transmitted edge-aligned. To capture this transmitted data using Virtex-4 FPGAs, either the
strobe or the data can be delayed. In this design, the read data is captured in the delayed
strobe domain and recaptured in the FPGA clock domain in the ISERDES. The received serial,
double data rate (DDR) read data is converted to 4-bit parallel single data rate (SDR) data at
half the frequency of the interface using the ISERDES. The differential strobe is placed on a
clock-capable IO pair in order to access the BUFIO clock resource. The BUFIO clocking
resource routes the delayed read DQS to its associated data ISERDES clock inputs. The write
data and strobe transmitted by the FPGA use the OSERDES. The OSERDES converts 4-bit
parallel data at half the frequency of the interface to DDR data at the interface frequency. The
controller, datapath, user interface, and all other FPGA slice logic are clocked at half the
frequency of the interface, resulting in improved design margin at frequencies of 267 MHz and
above.
Clocking
Scheme
The clocking scheme for this design includes one digital clock manager (DCM) and two phase-
matched clock dividers (PMCDs) as shown in
Figure 1
. The controller is clocked at half the
frequency of the interface using CLKdiv_0. Therefore, the address, bank address, and
command signals (RAS_L, CAS_L, and WE_L) are asserted for two clock cycles (known as
"2T" timing), of the fast memory interface clock. The control signals (CS_L, CKE, and ODT) are
twice the rate (DDR) of the half frequency clock CLKdiv_0, ensuring that the control signals are
asserted for just one clock cycle of the fast memory interface clock. The clock is forwarded to
the external memory device using the Output Dual Data Rate (ODDR) flip-flops in the Virtex-4
I/O. This forwarded clock is 180 degrees out of phase with CLKfast_0.
Figure 2
shows the
command and control timing diagram.
Application Note: Virtex-4 Series
XAPP721 (v1.3) February 2, 2006
High-Performance DDR2 SDRAM
Interface Data Capture Using ISERDES
and OSERDES
Author: Maria George
R
March 2006
Memory Interfaces Solution Guide
55
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Summary
Write Datapath R Write Datapath The write datapath uses the built-in OSERDES available in every Virtex-4 I/O. The OSERDES transmits the data (DQ) and strobe (DQS) signals. The memory specification requires DQS tobe transmitted center-aligned with DQ. The strobe (DQS) forwarded to the memory is 180 d...
Write Datapath R Figure 3: Write Data Transmitted Using OSERDES Figure 4: Write Strobe (DQS) and Data (DQ) Timing for a Write Latency of Four D1 D2 D3 D4 CLKDIV CLK CLKdiv_90 CLKfast_90 OSERDES DQ IOB ChipSync TM Circuit Write Data Words 0-3 X721_03_080305 CLKfast_0 Clock Forwarded to Memory Device ...
Write Datapath R Write Timing Analysis Table 1 shows the write timing analysis for an interface at 333 MHz (667 Mb/s). Table 1: Write Timing Analysis at 333 MHz Uncertainty Parameters Value Uncertainties before DQS Uncertainties after DQS Meaning T CLOCK 3000 Clock period. T MEMORY_DLL_DUTY_CYCLE_DI...
