Xilinx 1.8 - Manuals

Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 5 UG343 June 27, 2008 R Preface About This Guide The Endpoint Block Plus for PCI Express® Getting Started Guide provides information about generating an Endpoint Block Plus for PCI Express (PCIe ® ) core, customizing and simulating the core usi...

6 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Preface: About This Guide R Online Document The following linking conventions are used in this document: Italic font References to other manuals See the User Guide for details. Emphasis in text If a wire is drawn so that i...

Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 7 UG343 June 27, 2008 R Chapter 1 Introduction The Endpoint Block Plus for PCI Express is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex™-5 FPGA devices. This core supports Verilog® and VHDL. The...

8 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 1: Introduction R performance, pipelined FPGA designs using Xilinx implementation software and User Constraints Files (UCF) is recommended. Additional Core Resources For detailed information and updates about the c...

Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 9 UG343 June 27, 2008 Feedback R Document For comments or suggestions about this document, please submit a WebCase from www.xilinx.com/support . Be sure to include the following information: • Document title • Document number • Page number(s) t...

Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 11 UG343 June 27, 2008 R Chapter 2 Licensing the Core This chapter provided licensing options for the Endpoint Block Plus for PCI Express core, which you must do before using the core in your designs. The core is provided under the terms of the...

12 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 2: Licensing the Core R Obtaining Your License Simulation Only Evaluation License The Simulation Only Evaluation license is provided with the CORE Generator system and requires no license file. Obtaining a Full Li...

Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 13 UG343 June 27, 2008 R Chapter 3 Quickstart Example Design This chapter provides an overview of the Endpoint Block Plus for PCI Express example design (both single and dual core) and instructions for generating the core. It also includes info...

Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 15 UG343 June 27, 2008 Overview R Implementation Design Overview The implementation design consists of a simple PIO example that can accept read and write transactions and respond to requests, as illustrated in Figure 3-2 . Source code for the ...

16 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quickstart Example Design R Generating the Core To generate a core using the default values in the CORE Generator Graphical User Interface (GUI), do the following: 1. Start the CORE Generator. For help starting...

18 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quickstart Example Design R Simulating the Example Design The example design provides a quick way to simulate and observe the behavior of the core. The simulation environment provided with the Block Plus core p...

Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 19 UG343 June 27, 2008 Implementing the Example Design R 2. Run the script that corresponds to your simulation tool using one of the following: • VCS : simulate_vcs.sh • Cadence IUS : simulate_ncsim.sh • ModelSim : vsim -do simulate_mti.do Impl...

20 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quickstart Example Design R • routed.sdf Timing model Standard Delay File. • mapped.mrp Xilinx map report. • routed.par Xilinx place and route report. • routed.twr Xilinx timing analysis report. The script file...

26 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quickstart Example Design R Dual Core Directory Structure and File Contents When generating the Block Plus core with the Virtex-5 FX70T-FF1136 (XC5VFX70T-FF1136) FPGA, the PIO example design source files and sc...

Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 29 UG343 June 27, 2008 R Appendix Additional Design Considerations Package Constraints This appendix describes design considerations specific to the Endpoint Block Plus for PCIe core. Table A-1 lists the smallest supported device and interface ...