Page 2 - Revision History
www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduc...
Page 3 - Preface: About This Guide; Table of Contents
Endpoint Block Plus v1.8 for PCI Express www.xilinx.com UG343 June 27, 2008 Preface: About This Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Conventions . . . . . . . . . . . . . . . . . . ....
Page 4 - Appendix: Additional Design Considerations
www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Dual Core Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Dual Core Directory Structure and File Contents . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5 - Preface; About This Guide; Contents; Conventions; Typographical
Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 5 UG343 June 27, 2008 R Preface About This Guide The Endpoint Block Plus for PCI Express® Getting Started Guide provides information about generating an Endpoint Block Plus for PCI Express (PCIe ® ) core, customizing and simulating the core usi...
Page 6 - Online Document
6 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Preface: About This Guide R Online Document The following linking conventions are used in this document: Italic font References to other manuals See the User Guide for details. Emphasis in text If a wire is drawn so that i...
Page 7 - Chapter 1; Introduction; About the Core; System Requirements; Recommended Design Experience
Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 7 UG343 June 27, 2008 R Chapter 1 Introduction The Endpoint Block Plus for PCI Express is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex™-5 FPGA devices. This core supports Verilog® and VHDL. The...
Page 8 - Additional Core Resources; Technical Support; Core
8 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 1: Introduction R performance, pipelined FPGA designs using Xilinx implementation software and User Constraints Files (UCF) is recommended. Additional Core Resources For detailed information and updates about the c...
Page 9 - Document
Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 9 UG343 June 27, 2008 Feedback R Document For comments or suggestions about this document, please submit a WebCase from www.xilinx.com/support . Be sure to include the following information: • Document title • Document number • Page number(s) t...
Page 11 - Chapter 2; Licensing the Core; Before you Begin; License Options; Simulation Only
Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 11 UG343 June 27, 2008 R Chapter 2 Licensing the Core This chapter provided licensing options for the Endpoint Block Plus for PCI Express core, which you must do before using the core in your designs. The core is provided under the terms of the...
Page 12 - Obtaining Your License; Installing Your License File
12 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 2: Licensing the Core R Obtaining Your License Simulation Only Evaluation License The Simulation Only Evaluation license is provided with the CORE Generator system and requires no license file. Obtaining a Full Li...
Page 13 - Chapter 3; Quickstart Example Design; Overview; Simulation Design Overview
Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 13 UG343 June 27, 2008 R Chapter 3 Quickstart Example Design This chapter provides an overview of the Endpoint Block Plus for PCI Express example design (both single and dual core) and instructions for generating the core. It also includes info...
Page 15 - Implementation Design Overview; Example Design Elements
Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 15 UG343 June 27, 2008 Overview R Implementation Design Overview The implementation design consists of a simple PIO example that can accept read and write transactions and respond to requests, as illustrated in Figure 3-2 . Source code for the ...
Page 16 - Generating the Core
16 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quickstart Example Design R Generating the Core To generate a core using the default values in the CORE Generator Graphical User Interface (GUI), do the following: 1. Start the CORE Generator. For help starting...
Page 18 - Simulating the Example Design; Setting up for Simulation; Simulator Requirements; Running the Simulation; For Cadence IUS
18 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quickstart Example Design R Simulating the Example Design The example design provides a quick way to simulate and observe the behavior of the core. The simulation environment provided with the Block Plus core p...
Page 19 - Implementing the Example Design
Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 19 UG343 June 27, 2008 Implementing the Example Design R 2. Run the script that corresponds to your simulation tool using one of the following: • VCS : simulate_vcs.sh • Cadence IUS : simulate_ncsim.sh • ModelSim : vsim -do simulate_mti.do Impl...
Page 20 - Directory Structure and File Contents; Example Design
20 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quickstart Example Design R • routed.sdf Timing model Standard Delay File. • mapped.mrp Xilinx map report. • routed.par Xilinx place and route report. • routed.twr Xilinx timing analysis report. The script file...
Page 26 - Dual Core Directory Structure and File Contents
26 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quickstart Example Design R Dual Core Directory Structure and File Contents When generating the Block Plus core with the Virtex-5 FX70T-FF1136 (XC5VFX70T-FF1136) FPGA, the PIO example design source files and sc...
Page 29 - Appendix; Additional Design Considerations
Endpoint Block Plus v1.8 for PCI Express www.xilinx.com 29 UG343 June 27, 2008 R Appendix Additional Design Considerations Package Constraints This appendix describes design considerations specific to the Endpoint Block Plus for PCIe core. Table A-1 lists the smallest supported device and interface ...
