National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ - Manuals

Page 5 - Contents; About This Manual; xi

© National Instruments Corporation v Lab-PC+ User Manual Contents About This Manual ........................................................................................................... xi Organization of the Lab-PC+ User Manual ....................................................................

Page 8 - Figures

Contents Lab-PC+ User Manual viii © National Instruments Corporation Figures Figure 1-1. The Relationship between the Programming Environment,NI-DAQ, and Your Hardware ............................................................................ 1-3 Figure 2-1. Parts Locator Diagram ....................

Page 9 - Tables

Contents © National Instruments Corporation ix Lab-PC+ User Manual Tables Table 2-1. PC Bus Interface Factory Settings ..................................................................... 2-3 Table 2-2. Switch Settings with Corresponding Base I/O Address andBase I/O Address Space .....................

Page 11 - Conventions Used in This Manual; The following conventions appear in this manual.; bold; bold italic; monospace

About This Manual Lab-PC+ User Manual xii © National Instruments Corporation • The Glossary contains an alphabetical list and description of terms used in this manual,including abbreviations, acronyms, metric prefixes, mnemonics, and symbols. • The Index contains an alphabetical list of key terms an...

Page 12 - National Instruments Documentation

About this Manual © National Instruments Corporation xiii Lab-PC+ User Manual National Instruments Documentation The Lab-PC+ User Manual is one piece of the documentation set for your DAQ system. Youcould have any of several types of manuals depending on the hardware and software in yoursystem. Use ...

Page 13 - What You Need to Get Started; One of the following software packages and documentation:

© National Instruments Corporation 1-1 Lab-PC+ User Manual Chapter 1Introduction This chapter describes the Lab-PC+; lists what you need to get started; describes the optionalsoftware and optional equipment; and explains how to unpack the Lab-PC+. About the Lab-PC+ The Lab-PC+ is a low-cost multifun...

Page 14 - Software Programming Choices; LabVIEW and LabWindows/CVI Application Software

Introduction Chapter 1 Lab-PC+ User Manual 1-2 © National Instruments Corporation Software Programming Choices There are several options to choose from when programming your National Instruments DAQand SCXI hardware. You can use LabVIEW, LabWindows/CVI, NI-DAQ, or register-levelprogramming. LabVIEW ...

Page 15 - and Your Hardware; Register-Level Programming

Chapter 1 Introduction © National Instruments Corporation 1-3 Lab-PC+ User Manual NI-DAQ also internally addresses many of the complex issues between the computer and theDAQ hardware such as programming interrupts and DMA controllers. NI-DAQ maintains aconsistent software interface among its differe...

Page 16 - Optional Equipment; Cables and cable assemblies, shielded and ribbon; Unpacking

Introduction Chapter 1 Lab-PC+ User Manual 1-4 © National Instruments Corporation Optional Equipment National Instruments offers a variety of products to use with your Lab-PC+ board, includingcables, connector blocks, and other accessories, as follows: • Cables and cable assemblies, shielded and rib...

Page 17 - Board Configuration; PC Bus Interface

© National Instruments Corporation 2-1 Lab-PC+ User Manual Chapter 2Configuration and Installation This chapter describes the Lab-PC+ jumper configuration and installation of the Lab-PC+ boardin your computer. Board Configuration The Lab-PC+ contains six jumpers and one DIP switch to configure the P...

Page 19 - Table 2-1. PC Bus Interface Factory Settings; Default Settings; DMA Channel; Base I/O Address Selection

Chapter 2 Configuration and Installation © National Instruments Corporation 2-3 Lab-PC+ User Manual Table 2-1. PC Bus Interface Factory Settings Lab-PC+ Board Default Settings Hardware Implementation Base I/O Address Hex 260 A5 1 2 3 4 5 ON OFF U1 A9 A8 A7 A6 DMA Channel DMA Channel 3(factory settin...

Page 21 - Table 2-2. Switch Settings with Corresponding Base I/O Address; Switch Setting

Chapter 2 Configuration and Installation © National Instruments Corporation 2-5 Lab-PC+ User Manual Table 2-2. Switch Settings with Corresponding Base I/O Address and Base I/O Address Space Switch Setting A9 A8 A7 A6 A5 Base I/O Address (hex) Base I/O Address Space Used (hex) 0 0 0 0 0 000 000 - 01F...

Page 22 - DMA Channel Selection; Each DMA channel consists of two signal lines as shown in Table 2-3.

Configuration and Installation Chapter 2 Lab-PC+ User Manual 2-6 © National Instruments Corporation DMA Channel Selection The Lab-PC+ uses the DMA channel selected by jumpers on W6 (see Figure 2-1). The Lab-PC+is set at the factory to use DMA Channel 3. This is the default DMA channel used by theLab...

Page 23 - Figure 2-4. DMA Jumper Settings for Disabling DMA Transfers; Interrupt Selection; most IBM PC and compatible computers.

Chapter 2 Configuration and Installation © National Instruments Corporation 2-7 Lab-PC+ User Manual • • • • • • • • • • • • • • • • DACK* DRQ W6 1 2 3 Figure 2-4. DMA Jumper Settings for Disabling DMA Transfers Interrupt Selection The Lab-PC+ board can connect to any one of the six interrupt lines o...

Page 24 - Figure 2-6. Interrupt Jumper Setting for Disabling Interrupts; Analog I/O Configuration; Referenced single-ended input mode

Configuration and Installation Chapter 2 Lab-PC+ User Manual 2-8 © National Instruments Corporation If you do not want to use interrupts, place the jumper on W5 in the position shown in Figure 2-6.This setting disables the Lab-PC+ from asserting an interrupt line on the PC I/O channel. • • • • • • •...

Page 25 - Parameter; Analog Output Configuration; Bipolar Output Selection

Chapter 2 Configuration and Installation © National Instruments Corporation 2-9 Lab-PC+ User Manual Table 2-4. Analog I/O Jumper Settings Parameter Configuration Jumper Settings Output CH0 Polarity Bipolar: ± 5 V (factory setting) Unipolar: 0 to 10 V W1: A-BW1: B-C Output CH1 Polarity Bipolar: ± 5 V...

Page 26 - Unipolar Output Selection; Analog Output Channel 0; Figure 2-8. Unipolar Output Jumper Configuration; Analog Input Configuration; Input Mode

Configuration and Installation Chapter 2 Lab-PC+ User Manual 2-10 © National Instruments Corporation Unipolar Output Selection You can select the unipolar (0 V to 10 V) output configuration for either analog output channelby setting the following jumpers: Analog Output Channel 0 W1 B-C Analog Output...

Page 27 - Configuration; /D bit as described in the Command

Chapter 2 Configuration and Installation © National Instruments Corporation 2-11 Lab-PC+ User Manual Table 2-5. Input Configurations Available for the Lab-PC+ Configuration Description DIFF Differential configuration provides four differential inputs with thepositive (+) input of the instrumentation...

Page 28 - This configuration is shown in Figure 2-9.; __ /D bit as described in the Command Register 4 bit description in

Configuration and Installation Chapter 2 Lab-PC+ User Manual 2-12 © National Instruments Corporation This configuration is shown in Figure 2-9. W4 • A B C RSE NRSE/DIFF Figure 2-9. DIFF Input Configuration Considerations in using the DIFF configuration are discussed in Chapter 3, Signal Connections....

Page 29 - Analog Input Polarity Configuration; Bipolar Input Selection

Chapter 2 Configuration and Installation © National Instruments Corporation 2-13 Lab-PC+ User Manual NRSE Input (Eight Channels) NRSE input means that all input signals are referenced to the same common mode voltage,which is allowed to float with respect to the analog ground of the Lab-PC+ board. Th...

Page 30 - Unipolar Input Selection; Analog Input

Configuration and Installation Chapter 2 Lab-PC+ User Manual 2-14 © National Instruments Corporation • • • A B C W3 B U Figure 2-12. Bipolar Input Jumper Configuration (Factory Setting) Unipolar Input Selection You can select the unipolar (0 to 10 V) input configuration by setting the following jump...

Page 31 - Hardware Installation; Remove the expansion slot cover on the back panel of the computer.

Chapter 2 Configuration and Installation © National Instruments Corporation 2-15 Lab-PC+ User Manual Hardware Installation The Lab-PC+ can be installed in any available 8-bit or 16-bit expansion slot in your computer.After you have changed (if necessary), verified, and recorded the switches and jump...

Page 32 - I/O Connector Pin Description; liable for any damages resulting from any such signal

© National Instruments Corporation 3-1 Lab-PC+ User Manual Chapter 3Signal Connections This chapter describes how to make input and output signal connections to your Lab-PC+ boardvia the board I/O connector. I/O Connector Pin Description Figure 3-1 shows the pin assignments for the Lab-PC+ I/O conne...

Page 33 - Signal Connection Descriptions

Signal Connections Chapter 3 Lab-PC+ User Manual 3-2 © National Instruments Corporation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2...

Page 34 - Pin

Chapter 3 Signal Connections © National Instruments Corporation 3-3 Lab-PC+ User Manual Pin Signal Name Description 1-8 ACH0 through ACH7 Analog input Channels 0 through 7 (single-ended). 9 AISENSE/AIGND Analog input ground in RSE mode, AISENSE in NRSEmode. Bi-directional. 10 DAC0 OUT Voltage output...

Page 35 - Analog Input Signal Connections; liable for any damages resulting from

Signal Connections Chapter 3 Lab-PC+ User Manual 3-4 © National Instruments Corporation The connector pins can be grouped into analog input signal pins, analog output signal pins,digital I/O signal pins, and timing I/O signal pins. Signal connection guidelines for each of thesegroups are included la...

Page 36 - Types of Signal Sources; Floating Signal Sources

Chapter 3 Signal Connections © National Instruments Corporation 3-5 Lab-PC+ User Manual - + InstrumentationAmplifier + - MeasuredVoltage Vm = [Vin+ - Vin-] * GAIN Vin- Vm Vin+ Figure 3-2. Lab-PC+ Instrumentation Amplifier The Lab-PC+ instrumentation amplifier applies gain, common-mode voltage reject...

Page 37 - Ground-Referenced Signal Sources; Input Configurations; and Floating Signal Sources; Type of Signal; Floating; Differential Connection Considerations (DIFF Configuration)

Signal Connections Chapter 3 Lab-PC+ User Manual 3-6 © National Instruments Corporation the measured input signal varies or appears to float. An instrument or device that provides anisolated output falls into the floating signal source category. Ground-Referenced Signal Sources A ground-referenced s...

Page 38 - Leads connecting the signals to the Lab-PC+ are greater than 15 ft.; Differential Connections for Grounded Signal Sources

Chapter 3 Signal Connections © National Instruments Corporation 3-7 Lab-PC+ User Manual When the Lab-PC+ is configured for DIFF input, each signal uses two of the multiplexer inputs–one for the signal and one for its reference signal. Therefore, only four analog input channels areavailable when usin...

Page 39 - Differential Connections for Floating Signal Sources

Signal Connections Chapter 3 Lab-PC+ User Manual 3-8 © National Instruments Corporation + - + GroundedSignalSource V m MeasuredVoltage - V s - + I/O Connector Lab-PC+ Board in DIFF Configuration 1 3 5 7 2 4 6 8 9 CommonModeNoise,GroundPotential,and so on ACH 0 AGND 11 AISENSE/AIGND ACH 2 ACH 4 ACH 6...

Page 40 - Figure 3-4. Differential Input Connections for Floating Sources

Chapter 3 Signal Connections © National Instruments Corporation 3-9 Lab-PC+ User Manual + - + FloatingSignalSource V m MeasuredVoltage - V s - + I/O Connector Lab-PC+ Board in DIFF Configuration 1 3 5 7 2 4 6 8 9 100 k Ω BiasCurrentReturn Paths ACH 0 AGND 11 AISENSE/AIGND ACH 2 ACH 4 ACH 6 ACH 1 ACH...

Page 41 - Single-Ended Connection Considerations

Signal Connections Chapter 3 Lab-PC+ User Manual 3-10 © National Instruments Corporation Single-Ended Connection Considerations Single-ended connections are those in which all Lab-PC+ analog input signals are referenced toone common ground. The input signals are tied to the positive input of the ins...

Page 43 - Common-Mode Signal Rejection Considerations

Signal Connections Chapter 3 Lab-PC+ User Manual 3-12 © National Instruments Corporation ACH 0 V m MeasuredVoltage Common ModeNoise and so on AGND AISENSE/AIGND V s V cm - - + + - + - + I/O Connector Lab-PC+ Board in NRSE Input Configuration 1 2 3 8 9 11 Ground- Referenced Signal Source ACH 1 ACH 2 ...

Page 44 - Digital I/O Signal Connections

Chapter 3 Signal Connections © National Instruments Corporation 3-13 Lab-PC+ User Manual Pin 11, AGND, is the ground reference point for both analog output channels as well as analoginput. The following output ranges are available: Output signal range Bipolar input: ± 5 V * Unipolar input: 0 to 10 V...

Page 45 - Minimum

Signal Connections Chapter 3 Lab-PC+ User Manual 3-14 © National Instruments Corporation are connected to the digital lines PC<0..7> for digital I/O Port C. Pin 13, DGND, is the digitalground pin for all three digital I/O ports. The following specifications and ratings apply to the digital I/O...

Page 46 - Port C Pin Connections

Chapter 3 Signal Connections © National Instruments Corporation 3-15 Lab-PC+ User Manual 14 PA0 22 PB0 30 PC0 13 DGND Lab-PC+ Board Switch I/O Connector +5 V +5 V LED TTL Signal Port B PB<7..0> Port A PA<7..0> Port C PC<7..0> Figure 3-8. Digital I/O Connections In Figure 3-8, Port ...

Page 47 - *Indicates that the signal is active low.

Signal Connections Chapter 3 Lab-PC+ User Manual 3-16 © National Instruments Corporation Table 3-2. Port C Signal Assignments Programmable Mode Group A Group B PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Mode 0 I/O I/O I/O I/O I/O I/O I/O I/O Mode 1 Input I/O I/O IBFA STBA* INTRA STBB* IBFBB INTRB Mode 1 Output...

Page 48 - Name

Chapter 3 Signal Connections © National Instruments Corporation 3-17 Lab-PC+ User Manual Name Type Description (continued) OBF* Output Output buffer full–A low signal on this handshaking line indicatesthat data has been written from the specified port. INTR Output Interrupt request–This signal becom...

Page 49 - Mode 1 Input Timing; All timing values are in nanoseconds.

Signal Connections Chapter 3 Lab-PC+ User Manual 3-18 © National Instruments Corporation Mode 1 Input Timing The timing specifications for an input transfer in Mode 1 are as follows: DATA RD * INTR IBF STB * T1 T2 T4 T7 T6 T3 T5 Name Description Minimum Maximum T1 STB* pulse width 500 – T2 STB* = 0 ...

Page 50 - Mode 1 Output Timing

Chapter 3 Signal Connections © National Instruments Corporation 3-19 Lab-PC+ User Manual Mode 1 Output Timing The timing specifications for an output transfer in Mode 1 are as follows: WR* OBF* INTR ACK* DATA T1 T2 T3 T4 T5 T6 Name Description Minimum Maximum T1 WR* = 0 to INTR = 0 – 450 T2 WR* = 1 ...

Page 51 - Mode 2 Bidirectional Timing

Signal Connections Chapter 3 Lab-PC+ User Manual 3-20 © National Instruments Corporation Mode 2 Bidirectional Timing The timing specifications for bidirectional transfers in Mode 2 are as follows: T1 T6 T7 T3 T4 T10 T2 T5 T8 T9 WR * OBF * INTR ACK * STB * IBF RD * DATA Name Description Minimum Maxim...

Page 52 - Timing Connections; Data Acquisition Timing Connections

Chapter 3 Signal Connections © National Instruments Corporation 3-21 Lab-PC+ User Manual Timing Connections Pins 38 through 48 of the I/O connector are connections for timing I/O signals. The timing I/Oof the Lab-PC+ is designed around the 8253 Counter/Timer integrated circuit. Two of theseintegrate...

Page 53 - Figure 3-10. Posttrigger Data Acquisition Timing Case 1

Signal Connections Chapter 3 Lab-PC+ User Manual 3-22 © National Instruments Corporation and 3-11 illustrate two possible posttrigger data acquisition timing cases. In Figure 3-10, therising edge on EXTTRIG is sensed when the EXTCONV* input is high. Thus, the first A/Dconversion occurs on the second...

Page 54 - Figure 3-12. Pretrigger Data Acquisition Timing

Chapter 3 Signal Connections © National Instruments Corporation 3-23 Lab-PC+ User Manual If PRETRIG is set, EXTTRIG serves as a pretrigger signal. In pretrigger mode, A/D conversionsare enabled via software before a rising edge is sensed on the EXTTRIG input. However, thesample counter, Counter A1, ...

Page 55 - Figure 3-13. EXTUPDATE* Signal Timing for Updating DAC Output

Signal Connections Chapter 3 Lab-PC+ User Manual 3-24 © National Instruments Corporation text Minimum 50 nsec EXTUPDATE* DAC OUTPUTUPDATE CNTINT DACWRT text Figure 3-13. EXTUPDATE* Signal Timing for Updating DAC Output Since a rising edge on the EXTUPDATE* signal always sets the CNTINT bit in the St...

Page 57 - Figure 3-16. Frequency Measurement Application

Signal Connections Chapter 3 Lab-PC+ User Manual 3-26 © National Instruments Corporation counting after receiving a low-to-high edge. The time lapse since receiving the edge equals thecounter value difference (loaded value minus read value) multiplied by the CLK period. To perform frequency measurem...

Page 59 - Cabling

Signal Connections Chapter 3 Lab-PC+ User Manual 3-28 © National Instruments Corporation The GATE and OUT signals in Figure 3-17 are referenced to the rising edge of the CLK signal. Cabling National Instruments currently offers a cable termination accessory, the CB-50, for use with theLab-PC+ board....

Page 60 - Functional Overview

© National Instruments Corporation 4-1 Lab-PC+ User Manual Chapter 4Theory of Operation This chapter contains a functional overview of the Lab-PC+ and explains the operation of eachfunctional unit making up the Lab-PC+. This chapter also explains the basic operation of theLab-PC+ circuitry. Function...

Page 61 - The following are the major components making up the Lab-PC+ board:; PC I/O Channel Interface Circuitry

Theory of Operation Chapter 4 Lab-PC+ User Manual 4-2 © National Instruments Corporation The following are the major components making up the Lab-PC+ board: • PC I/O channel interface circuitry • Analog input and data acquisition circuitry • Analog output circuitry • Digital I/O circuitry • Timing I...

Page 62 - When an A/D conversion is available to be read from FIFO

Chapter 4 Theory of Operation © National Instruments Corporation 4-3 Lab-PC+ User Manual Address Bus Address Latches Address Decoder TimingInterface Data Buffers DMAControl InterruptControl Control Lines Data Bus DMA REQ DMA ACK IRQ Register Selects Read and Write Signals Internal Data Bus DMA Reque...

Page 63 - When a digital I/O port is ready to transfer data; Analog Input and Data Acquisition Circuitry

Theory of Operation Chapter 4 Lab-PC+ User Manual 4-4 © National Instruments Corporation • When a digital I/O port is ready to transfer data • When a rising edge signal is detected on Counter A2 output or on the EXTUPDATE line Each one of these interrupts is individually enabled and cleared. The DMA...

Page 64 - Analog Input Circuitry

Chapter 4 Theory of Operation © National Instruments Corporation 4-5 Lab-PC+ User Manual Analog Input Circuitry The analog input circuitry consists of two CMOS analog input multiplexers, a software-programmable gain amplifier, a 12-bit ADC, and a 12-bit FIFO memory that is sign-extended to16 bits. O...

Page 65 - Single-Channel Data Acquisition

Theory of Operation Chapter 4 Lab-PC+ User Manual 4-6 © National Instruments Corporation (scanned) data acquisition in two modes–continuous and interval. The Lab-PC+ uses a counterto switch between analog input channels automatically during scanned data acquisition. Data acquisition timing consists ...

Page 66 - Data Acquisition Rates; Table 4-1. Analog Input Settling Time Versus Gain; Gain Setting; s maximum

Chapter 4 Theory of Operation © National Instruments Corporation 4-7 Lab-PC+ User Manual You must initialize two additional counters to operate in interval acquisition mode. In single-channel interval acquisition mode, the Lab-PC+ samples a single channel a programmablenumber of times, waits for the...

Page 67 - Single Channel

Theory of Operation Chapter 4 Lab-PC+ User Manual 4-8 © National Instruments Corporation Table 4-2. Lab-PC+ Maximum Recommended Data Acquisition Rates Acquisition Mode Gain Setting Rate Single Channel 12, 5, 10, 20, 50, 100 83.3 ksamples/s71.4 ksamples/s* Multiple Channel 12, 5, 10, 20, 50 100 83.3 ...

Page 68 - Analog Output Circuitry; Figure 4-4. Analog Output Circuitry Block Diagram

Chapter 4 Theory of Operation © National Instruments Corporation 4-9 Lab-PC+ User Manual Analog Output Circuitry The Lab-PC+ provides two channels of 12-bit D/A output. Each analog output channel canprovide unipolar or bipolar output. Figure 4-4 shows a block diagram of the analog outputcircuitry. D...

Page 69 - Digital I/O Circuitry

Theory of Operation Chapter 4 Lab-PC+ User Manual 4-10 © National Instruments Corporation Each DAC channel can be jumper-programmed for either a unipolar voltage output or a bipolarvoltage output range. A unipolar output gives an output voltage range of 0.0000 V to +9.9976 V.A bipolar output gives a...

Page 74 - Calibration Equipment Requirements

© National Instruments Corporation 5-1 Lab-PC+ User Manual Chapter 5Calibration This chapter discusses the calibration procedures for the Lab-PC+ analog input and analog outputcircuitry. The Lab-PC+ is calibrated at the factory before shipment. In order to maintain the 12-bitaccuracy of the Lab-PC+ ...

Page 75 - Calibration Trimpots

Calibration Chapter 5 Lab-PC+ User Manual 5-2 © National Instruments Corporation Calibration Trimpots The Lab-PC+ has six trimpots for calibration. The location of these trimpots on the Lab-PC+board is shown in the partial diagram of the board in Figure 5-1. 1 2 3 4 5 6 7 1 R1 3 R3 5 R5 7 R7 2 R2 4 ...

Page 76 - Analog Input Calibration; Offset errors

Chapter 5 Calibration © National Instruments Corporation 5-3 Lab-PC+ User Manual Analog Input Calibration To null out error sources that compromise the quality of measurements, you must calibrate theanalog input circuitry by adjusting the following potential sources of error: • Offset errors • Gain ...

Page 77 - Input Range

Calibration Chapter 5 Lab-PC+ User Manual 5-4 © National Instruments Corporation The voltages corresponding to V -fs , which is the most negative voltage that the ADC can read, V +fs - 1, which is the most positive voltage the ADC can read, and 1 LSB, which is the voltage corresponding to one count ...

Page 78 - Unipolar Input Calibration Procedure; Input Offset Calibration

Chapter 5 Calibration © National Instruments Corporation 5-5 Lab-PC+ User Manual later for software offset correction of the data at gains other than 1, thus eliminating the needto perform the input offset recalibration when a different gain is used. The softwarecorrection consists of subtracting th...

Page 79 - Analog Output Calibration; Analog output offset error

Calibration Chapter 5 Lab-PC+ User Manual 5-6 © National Instruments Corporation 3. Gain Calibration Adjust the analog input gain by applying an input voltage across ACH0 andAISENSE/AIGND. This input voltage is +9.99634 V or V +fs - 1.5 LSB. a. Connect the calibration voltage (+9.99634 V) across ACH...

Page 81 - Unipolar Output Calibration Procedure; Adjust the Analog Output Gain; For analog output Channel 0:

Calibration Chapter 5 Lab-PC+ User Manual 5-8 © National Instruments Corporation Unipolar Output Calibration Procedure If your analog output channel is configured for unipolar output, which has an output range of 0 to+10 V, then offset calibration is not needed. Calibrate your board by completing th...

Page 82 - Board Gain

© National Instruments Corporation A-1 Lab-PC+ User Manual Appendix ASpecifications This appendix lists the specifications of the Lab-PC+. These specifications are typical at 25 ° C unless otherwise stated. The operating temperature range is 0 ° to 70 ° C. Analog Input Input CharacteristicsNumber of...

Page 83 - in parallel with 45 pF; Gain; minutes

Specifications Appendix A Lab-PC+ User Manual A-2 © National Instruments Corporation Amplifier CharacteristicsInput impedance ............................................ 0.1 G Ω in parallel with 45 pF Input bias current .......................................... 150 pA CMRR ...........................

Page 84 - Explanation of Analog Input Specifications

Appendix A Specifications © National Instruments Corporation A-3 Lab-PC+ User Manual Explanation of Analog Input Specifications Relative accuracy is a measure of the linearity of an ADC. However, relative accuracy is atighter specification than a nonlinearity specification. Relative accuracy indicat...

Page 85 - Analog Output; Explanation of Analog Output Specifications

Specifications Appendix A Lab-PC+ User Manual A-4 © National Instruments Corporation Analog Output Output CharacteristicsNumber of channels ...................................... 2 Resolution ..................................................... 12 bits, 1 in 4,096 Type of DAC .........................

Page 86 - Level

Appendix A Specifications © National Instruments Corporation A-5 Lab-PC+ User Manual Differential nonlinearity (DNL) in a D/A system is a measure of deviation of code width from1 LSB. In this case, code width is the difference between the analog values produced byconsecutive digital codes. A specifi...

Page 87 - Triggers; Digital Trigger; Bus Interface

Specifications Appendix A Lab-PC+ User Manual A-6 © National Instruments Corporation Digital logic levels ........................................ Level Min Max Input low voltage Input high voltage -0.3 V 2.2 V 0.8 V5.3 V Output low voltage (I out = 4 mA) Output high voltage (I out = -1 mA) - 3.7 V ...

Page 117 - Register Map

© National Instruments Corporation D-1 Lab-PC+ User Manual Appendix DRegister Map and Descriptions This appendix describes in detail the address and function of each of the Lab-PC+ registers. Note: If you plan to use a programming software package such as NI-DAQ, NI-DSP,LabVIEW, or LabWindows/CVI wi...

Page 118 - Register Name

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-2 © National Instruments Corporation Table D-1. Lab-PC+ Register Map Register Name Offset Address (Hex) Type Size Configuration and Status Register Group Command Register 1 00 Write-only 8-bit Status Register 00 Read-only 8-bit Command R...

Page 119 - Register Sizes; Register Description; Register Description Format

Appendix D Register Map and Descriptions © National Instruments Corporation D-3 Lab-PC+ User Manual Register Sizes The Lab-PC+ registers are 8-bit registers. To transfer 16-bit data, two consecutive I/O readingsor writings are needed. For example, to read the 16-bit A/D conversion result, two consec...

Page 120 - Configuration and Status Register Group

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-4 © National Instruments Corporation Configuration and Status Register Group The five registers making up the Configuration and Status Register Group allow general controland monitoring of the Lab-PC+ A/D and D/A circuitry. Command Regis...

Page 121 - Command Register 1; Bit; SCANEN; Selected Gain

Appendix D Register Map and Descriptions © National Instruments Corporation D-5 Lab-PC+ User Manual Command Register 1 Command Register 1 indicates the input channel to be read, the gain for the analog inputcircuitry, and the range of the input signal (unipolar or bipolar). Address: Base address + 0...

Page 122 - TWOSCMP

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-6 © National Instruments Corporation Bit Name Description (continued) 3 TWOSCMP This bit selects the format of the coding of the output of the ADC.If this bit is set, the 12-bit data from the ADC is sign-extended to16 bits. If this bit i...

Page 123 - Status Register; EXTGATA0

Appendix D Register Map and Descriptions © National Instruments Corporation D-7 Lab-PC+ User Manual Status Register The Status Register indicates the status of the current A/D conversion. The bits in this registerdetermine if a conversion is being performed or if data is available, whether any error...

Page 124 - OVERRUN

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-8 © National Instruments Corporation Bit Name Description (continued) 1 OVERRUN This bit indicates if an overrun error has occurred. If this bit iscleared, no error occurred. This bit is set if a convert command isissued to the ADC while...

Page 125 - Command Register 2; TBSEL

Appendix D Register Map and Descriptions © National Instruments Corporation D-9 Lab-PC+ User Manual Command Register 2 Command Register 2 contains eight bits that control Lab-PC+ analog input trigger modes andanalog output modes. Address: Base address + 01 (hex) Type: Write-only Word Size: 8-bit Bit...

Page 126 - SWTRIG

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-10 © National Instruments Corporation Bit Name Description (continued) 2 SWTRIG This bit enables and disables a data acquisition operation that iscontrolled by Counter A0 and Counter A1. If Counter A0 isprogrammed for data acquisition, w...

Page 127 - Command Register 3; FIFOINTEN

Appendix D Register Map and Descriptions © National Instruments Corporation D-11 Lab-PC+ User Manual Command Register 3 The Command Register 3 contains six bits that enable and disable the interrupts and DMAoperation. Address: Base address + 02 (hex) Type: Write-only Word Size: 8-bit Bit Map: 7 6 5 ...

Page 128 - DIOINTEN

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-12 © National Instruments Corporation Bit Name Description (continued) 1 DIOINTEN This bit enables or disables generation of an interrupt when eitherPort A or Port B is ready to transfer data, and an interrupt requestis set via PC3 or PC...

Page 129 - ECLKRCV

Appendix D Register Map and Descriptions © National Instruments Corporation D-13 Lab-PC+ User Manual Command Register 4 This register allows multiplexing of certain A/D conversion logic signals. This enables theinterval scanning and A/D conversion signals to be available at the I/O connector and all...

Page 130 - ECKDRV

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-14 © National Instruments Corporation Bit Name Description (continued) 2 ECKDRV This bit controls the direction of the EXTCONV* line on the I/OConnector. If this bit is clear, EXTCONV* is driven from the I/OConnector into the conversion ...

Page 131 - Analog Input Register Group

Appendix D Register Map and Descriptions © National Instruments Corporation D-15 Lab-PC+ User Manual Analog Input Register Group The four registers making up the Analog Input Register Group control the analog input circuitryand can be used to read the FIFO. Reading the FIFO Register returns stored A...

Page 132 - Straight binary mode; High Byte

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-16 © National Instruments Corporation A/D FIFO Register The 12-bit A/D conversion results are sign-extended to 16-bit data in either two's complement orstraight binary format and are stored into a 512-word deep A/D FIFO buffer. Two conse...

Page 134 - Not applicable, no bits used

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-18 © National Instruments Corporation A/D Clear Register The ADC can be reset by writing to this register. This operation clears the FIFO and loads thelast conversion value into the FIFO. All error bits in the Status Register are cleared...

Page 135 - Start Convert Register

Appendix D Register Map and Descriptions © National Instruments Corporation D-19 Lab-PC+ User Manual Start Convert Register Writing to the Start Convert Register location initiates an A/D conversion. Address: Base address + 03 (hex) Type: Write-only Word Size: 8-bit Bit Map: Not applicable, no bits ...

Page 136 - DMATC Interrupt Clear Register

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-20 © National Instruments Corporation DMATC Interrupt Clear Register Writing to the DMA Terminal Count (DMATC) Clear Register clears the interrupt requestasserted when a DMA terminal count pulse is detected. Address: Base address + 0A (h...

Page 137 - Analog Output Register Group

Appendix D Register Map and Descriptions © National Instruments Corporation D-21 Lab-PC+ User Manual Analog Output Register Group The four registers making up the Analog Output Register Group are used for loading the two12-bit DACs in the two analog output channels. DAC0 controls analog output Chann...

Page 138 - DACxL; DACxH

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-22 © National Instruments Corporation DAC0 Low-Byte (DAC0L), DAC0 High-Byte (DAC0H), DAC1 Low-Byte (DAC1L), andDAC1 High-Byte (DAC1H) Registers Writing to DAC0L and then to DAC0H loads the analog output Channel 0. Writing to DAC1Land the...

Page 139 - 253 Counter/Timer Register Groups A and B

Appendix D Register Map and Descriptions © National Instruments Corporation D-23 Lab-PC+ User Manual 8253 Counter/Timer Register Groups A and B The nine registers making up the two Counter/Timer Register Groups access the two onboard8253 Counter/Timers. Each 8253 has three counters. For convenience,...

Page 140 - Counter A0 Data Register

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-24 © National Instruments Corporation Counter A0 Data Register The Counter A0 Data Register is used for loading and reading back contents of8253(A) Counter 0. Address: Base address + 14 (hex) Type: Read-and-write Word Size: 8-bit Bit Map...

Page 141 - Counter A1 Data Register

Appendix D Register Map and Descriptions © National Instruments Corporation D-25 Lab-PC+ User Manual Counter A1 Data Register The Counter A1 Data Register is used for loading and reading back contents of8253(A) Counter 1. Address: Base address + 15 (hex) Type: Read-and-write Word Size: 8-bit Bit Map...

Page 142 - Counter A2 Data Register

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-26 © National Instruments Corporation Counter A2 Data Register The Counter A2 Data Register is used for loading and reading back contents of8253(A)Counter A2. Address: Base address + 16 (hex) Type: Read-and-write Word Size: 8-bit Bit Map...

Page 143 - Counter A Mode Register

Appendix D Register Map and Descriptions © National Instruments Corporation D-27 Lab-PC+ User Manual Counter A Mode Register The Counter A Mode Register determines the operation mode for each of the three counters onthe 8253(A) chip. The Counter A Mode Register selects the counter involved, its read...

Page 144 - Timer Interrupt Clear Register

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-28 © National Instruments Corporation Timer Interrupt Clear Register Writing to the Timer Interrupt Clear Register clears the interrupt request asserted when a lowpulse is detected on the Counter A2 output or on EXTUPDATE* line. Address:...

Page 145 - Counter B0 Data Register

Appendix D Register Map and Descriptions © National Instruments Corporation D-29 Lab-PC+ User Manual Counter B0 Data Register The Counter B0 Data Register is used for loading and reading back the contents of 8253(B)Counter 0. Address: Base address + 18 (hex) Type: Read-and-write Word Size: 8-bit Bit...

Page 146 - Counter B1 Data Register

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-30 © National Instruments Corporation Counter B1 Data Register The Counter B1 Data Register is used for loading and reading back the contents of 8253(B)Counter 1. Address: Base address + 19 (hex) Type: Read-and-write Word Size: 8-bit Bit...

Page 147 - Counter B2 Data Register

Appendix D Register Map and Descriptions © National Instruments Corporation D-31 Lab-PC+ User Manual Counter B2 Data Register The Counter B2 Data Register is used for loading and reading back the contents of 8253(B)Counter 2. Address: Base address + 1A (hex) Type: Read-and-write Word Size: 8-bit Bit...

Page 148 - Counter B Mode Register

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-32 © National Instruments Corporation Counter B Mode Register The Counter B Mode Register determines the operation mode for each of the three counters onthe 8253(B) chip. The Counter B Mode Register selects the counter involved, its read...

Page 149 - 255A Digital I/O Register Group

Appendix D Register Map and Descriptions © National Instruments Corporation D-33 Lab-PC+ User Manual 8255A Digital I/O Register Group Digital I/O on the Lab-PC+ uses an 8255A integrated circuit. The 8255A is a general-purposeperipheral interface containing 24 programmable I/O pins. These pins repres...

Page 150 - Port A Register

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-34 © National Instruments Corporation Port A Register Reading the Port A Register returns the logic state of the eight digital I/O lines constitutingPort A, that is, PA<0..7>. If Port A is configured for output, the Port A Register...

Page 151 - Port B Register

Appendix D Register Map and Descriptions © National Instruments Corporation D-35 Lab-PC+ User Manual Port B Register Reading the Port B Register returns the logic state of the eight digital I/O lines constitutingPort B, that is, PB<0..7>. If Port B is configured for output, the Port B Register...

Page 152 - Port C Register

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-36 © National Instruments Corporation Port C Register Port C is special in the sense that it can be used as an 8-bit I/O port like Port A and Port B ifneither Port A nor Port B is used in handshaking (latched) mode. If either Port A or P...

Page 153 - Digital Control Register

Appendix D Register Map and Descriptions © National Instruments Corporation D-37 Lab-PC+ User Manual Digital Control Register The Digital Control Register can be used to configure Port A, Port B, and Port C as inputs oroutputs as well as selecting simple mode (basic I/O) or handshaking mode (strobed...

Page 154 - Interval Counter Register Group

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-38 © National Instruments Corporation Interval Counter Register Group The 8-bit Interval Counter is used only in the single-channel interval mode (SCANEN = 0 andINTSCAN = 1) and consists of two 8-bit registers–the Interval Counter Data R...

Page 155 - Interval Counter Data Register; Interval Counter count.

Appendix D Register Map and Descriptions © National Instruments Corporation D-39 Lab-PC+ User Manual Interval Counter Data Register The Interval Counter Data Register is loaded with the desired number of samples of a singlechannel that will be acquired between intervals. See Programming Multiple A/D...

Page 156 - Interval Counter Strobe Register; Each of these bits must be 0 for proper operation of the Lab-PC+.

Register Map and Descriptions Appendix D Lab-PC+ User Manual D-40 © National Instruments Corporation Interval Counter Strobe Register Writing to Interval Counter Strobe Register strobes the contents of the Interval Counter DataRegister into the Interval Counter. This action arms the Interval Counter...

Page 157 - Register Programming Considerations

© National Instruments Corporation E-1 Lab-PC+ User Manual Appendix ERegister-Level Programming This appendix contains important information about programming the Lab-PC+. Programming the Lab-PC+ involves writing to and reading from the various registers on theboard. The programming instructions inc...

Page 158 - This sequence leaves the Lab-PC+ circuitry in the following state:; Programming the Analog Input Circuitry

Register-Level Programming Appendix E Lab-PC+ User Manual E-2 © National Instruments Corporation 8. Write 00 (hex) to the DMATC Interrupt Clear Register. 9. Write 00 (hex) to the Timer Interrupt Clear Register. 10. Write 00 (hex) to the A/D Clear Register. 11. Read the data from the A/D FIFO Registe...

Page 159 - Analog Input Circuitry Programming Sequence

Appendix E Register-Level Programming © National Instruments Corporation E-3 Lab-PC+ User Manual Analog Input Circuitry Programming Sequence Programming the analog input circuitry for a single A/D conversion involves selecting the analoginput channel and gain, initiating an A/D conversion, and readi...

Page 160 - used for A/D timing, the DAVAIL bit should be set after 12; A/D FIFO Output Binary Modes

Register-Level Programming Appendix E Lab-PC+ User Manual E-4 © National Instruments Corporation The DAVAIL bit indicates whether one or more A/D conversion results are stored in the A/DFIFO. If the DAVAIL bit is cleared, the A/D FIFO is empty and reading the A/D FIFO Registerreturns meaningless dat...

Page 161 - Clearing the Analog Input Circuitry; Analog input error flags OVERFLOW and OVERRUN are cleared.

Appendix E Register-Level Programming © National Instruments Corporation E-5 Lab-PC+ User Manual Clearing the Analog Input Circuitry The analog input circuitry can be cleared by writing to the A/D Clear Register, which leaves theanalog input circuitry in the following state: • Analog input error fla...

Page 162 - s must be observed for data integrity.; Programming in Controlled Acquisition Mode; example, programming a timebase of 10

Register-Level Programming Appendix E Lab-PC+ User Manual E-6 © National Instruments Corporation Alternatively, a programmable timebase for Counter A0 is available through the use ofCounter B0. If the TBSEL bit in Command Register 1 is set, then the timebase for Counter A0 isCounter B0. Counter B0 h...

Page 163 - s. N is referred to as the sample interval, that

Appendix E Register-Level Programming © National Instruments Corporation E-7 Lab-PC+ User Manual 3. Program Counters A0 and A1. This step involves programming Counter A0 (the sample interval counter) in rate generatormode (Mode 2) and programming Counter A1 to interrupt on terminal count mode (Mode ...

Page 164 - Programming in Freerun Acquisition Mode

Register-Level Programming Appendix E Lab-PC+ User Manual E-8 © National Instruments Corporation Once the data acquisition operation is started, the operation must be serviced by reading theA/D FIFO Register every time an A/D conversion result becomes available. To do this,perform the following sequ...

Page 166 - Start and service the data acquisition operation.

Register-Level Programming Appendix E Lab-PC+ User Manual E-10 © National Instruments Corporation 4. Program Counter A1 to force OUT1 low. If OUT1 is high, Counter A0 is disabled. Write 70 (hex) to the Counter A Mode Register(select Counter A1, Mode 0) to force OUT1 low. Counter A0 can be used as th...

Page 168 - Using the EXTCONV* Signal to Initiate A/D Conversions; Posttrigger Mode

Register-Level Programming Appendix E Lab-PC+ User Manual E-12 © National Instruments Corporation Using the EXTCONV* Signal to Initiate A/D Conversions As mentioned earlier, A/D conversions can be initiated by a falling edge on either OUTA0 orEXTCONV*. Setting the GATA0 bit low disables conversions ...

Page 169 - To program the counters, use the following programming sequence:

Appendix E Register-Level Programming © National Instruments Corporation E-13 Lab-PC+ User Manual 3. Program Counter A0. Since a high-to-low transition on the Counter A0 output initiates an A/D conversion,Counter A0 output must be programmed to a high state. This ensures that Counter A0 doesnot caus...

Page 170 - Pretrigger Mode; Select analog input channel and gain and select pretrigger mode.

Register-Level Programming Appendix E Lab-PC+ User Manual E-14 © National Instruments Corporation Two error conditions may occur during a data acquisition operation: an overflow error or anoverrun error. These error conditions are reported through the Status Register and should bechecked every time ...

Page 171 - To program the counters, use the following programming sequence.

Appendix E Register-Level Programming © National Instruments Corporation E-15 Lab-PC+ User Manual 2. Program Counter A0. Since a high-to-low transition on the Counter A0 output initiates an A/D conversion,Counter A0 output must be programmed to a high state. This ensures that Counter A0 doesnot caus...

Page 172 - Start and service the data acquisition operation.

Register-Level Programming Appendix E Lab-PC+ User Manual E-16 © National Instruments Corporation 5. Start and service the data acquisition operation. To start the data acquisition operation, set the SWTRIG bit in Command Register 2. Afterthis setting, A/D conversions are initiated by a falling edge...

Page 175 - Use a software trigger to initiate the operation.; A/D Interrupt Programming; Two different interrupts are generated by the A/D circuitry:

Appendix E Register-Level Programming © National Instruments Corporation E-19 Lab-PC+ User Manual another N samples and the cycle repeats. The operation stops when the sample counter (CounterA1) decrements to 0. Use the following sequence to configure the Lab-PC+ for single-channelinterval acquisiti...

Page 176 - Programming DMA Operation; Register clears the DMATC bit in the Status Register.; Programming the Analog Output Circuitry

Register-Level Programming Appendix E Lab-PC+ User Manual E-20 © National Instruments Corporation To use the error interrupt, set the ERRINTEN bit in the Command Register 3. If this bit is set, aninterrupt is generated whenever the OVERFLOW or the OVERRUN bit in the Status Register isset. This inter...

Page 177 - Table E-3. Analog Output Voltage Versus Digital Code; Digital Code

Appendix E Register-Level Programming © National Instruments Corporation E-21 Lab-PC+ User Manual updated when a low level is detected on either EXTUPDATE* or OUTA2. If LDAC0 is set low,the analog output from DAC0 is updated as soon as the DAC0 Data Register is written to.LDAC1 controls the updating...

Page 178 - Table E-4. Analog Output Voltage Versus Digital Code; Interrupt Programming for the Analog Output Circuitry

Register-Level Programming Appendix E Lab-PC+ User Manual E-22 © National Instruments Corporation The following formula calculates the voltage output versus digital code for a bipolar analogoutput configuration and two’s complement coding: V out = 5.0 * (digital code) 2,048 The digital code in the a...

Page 179 - Programming the Digital I/O Circuitry; Register Descriptions and Programming Examples

Appendix E Register-Level Programming © National Instruments Corporation E-23 Lab-PC+ User Manual 3. Enable timer interrupts. Timer interrupts refer to the interrupts generated by rising edges on OUTA2 orEXTUPDATE*. A rising edge on OUTA2 or EXTUPDATE* sets the CNTINT bit high inthe Status Register....

Page 181 - Modes of Operation for the 8255A; The three basic modes of operation for the 8255A are as follows:; Control Words

Appendix E Register-Level Programming © National Instruments Corporation E-25 Lab-PC+ User Manual Modes of Operation for the 8255A The three basic modes of operation for the 8255A are as follows: • Mode 0 – Basic I/O • Mode 1 – Strobed I/O • Mode 2 – Bidirectional bus The 8255A also has a single bit...

Page 183 - Input

Appendix E Register-Level Programming © National Instruments Corporation E-27 Lab-PC+ User Manual Mode 1 This mode is used for transferring data with handshake signals. Ports A and B use the eight linesof Port C to generate or receive the handshake signals. This mode divides the ports into twogroups...

Page 185 - Programming Example; Example 1. Configure Port A as an input port in Mode 1:; Output

Appendix E Register-Level Programming © National Instruments Corporation E-29 Lab-PC+ User Manual Programming Example Example 1. Configure Port A as an input port in Mode 1: • Write B0 (hex) to the Digital Control Register. • Wait for bit 5 of Port C (IBFA) to be set, indicating that data has been l...

Page 186 - INTEA

Register-Level Programming Appendix E Lab-PC+ User Manual E-30 © National Instruments Corporation Port C status-word bit definitions for output (Port A and Port B): 7 6 5 4 3 2 1 0 OBFA* INTEA I/O I/O INTRA INTEB OBFB* INTRB Bit Name Description 7 OBFA* Output buffer full for Port A. Low indicates t...

Page 187 - Example 1. Configure Port A as an output port in Mode 1:

Appendix E Register-Level Programming © National Instruments Corporation E-31 Lab-PC+ User Manual Programming Example Example 1. Configure Port A as an output port in Mode 1: • Write A0 (hex) to the Digital Control Register. • Wait for bit 7 of Port C (OBFA*) to be cleared, indicating that the data ...

Page 188 - IBFA

Register-Level Programming Appendix E Lab-PC+ User Manual E-32 © National Instruments Corporation Port B direction1 = input0 = output Group B Mode0 = Mode 01 = Mode 1 1 X X 1/0 1 1/0 X 1/0 7 6 5 4 3 2 1 0 Port C bits (PC2-PC0) 1 = input0 = output During a Mode 2 data transfer, the status of the hand...

Page 190 - Single Bit Set/Reset Feature; Interrupt Programming for the Digital I/O Circuitry

Register-Level Programming Appendix E Lab-PC+ User Manual E-34 © National Instruments Corporation Single Bit Set/Reset Feature Any of the 8 bits of Port C can be set or reset with one control word. This feature is used togenerate status and control for Port A and Port B when operating in Mode 1 or M...

Page 191 - Branch Offices

© National Instruments Corporation F-1 Lab-PC+ User Manual Appendix FCustomer Communication For your convenience, this appendix contains forms to help you gather the information necessaryto help us solve technical problems you might have as well as a form you can use to comment onthe product documen...

Page 192 - Technical Support Form

Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware, and use the completedcopy of this form as a reference for your current configuration. Completing this form accurately before contactingNational Instruments for technical support helps ou...

Page 194 - Documentation Comment Form

Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. Thisinformation helps us provide quality products to meet your needs. Title: Lab-PC+ User Manual Edition Date: June 1996 Part Number: 320502B-01 Please comment on the completene...

Page 195 - Glossary; Prefix

© National Instruments Corporation Glossary-1 Lab-PC+ User Manual Glossary Prefix Meaning Value p- pico- 10 -12 n- nano- 10 -9 µ - micro- 10 -6 m- milli- 10 -3 k- kilo- 10 3 M- mega- 10 6 G- giga- 10 9 ° degrees Ω ohms % percent A amperes A/D analog-to-digital AC alternating current ADC A/D converte...

Page 197 - Index; Numbers

© National Instruments Corporation Index- 1 Lab-PC+ User Manual Index Numbers 2SDAC0 bit, D-92SDAC1 bit, D-9+5 V signal (table), 3-38253 Counter/Timer Register Groups A and B, D-23 to D-32 Counter A Mode Register description, D-27interrupt programming for analog output circuitry, E-22 to E-23 Counte...