National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ - Manual

National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+

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Table of Contents:

  • Page 5 – Contents; About This Manual; xi
  • Page 8 – Figures
  • Page 9 – Tables
  • Page 11 – Conventions Used in This Manual; The following conventions appear in this manual.; bold; bold italic; monospace
  • Page 12 – National Instruments Documentation
  • Page 13 – What You Need to Get Started; One of the following software packages and documentation:
  • Page 14 – Software Programming Choices; LabVIEW and LabWindows/CVI Application Software
  • Page 15 – and Your Hardware; Register-Level Programming
  • Page 16 – Optional Equipment; Cables and cable assemblies, shielded and ribbon; Unpacking
  • Page 17 – Board Configuration; PC Bus Interface
  • Page 19 – Table 2-1. PC Bus Interface Factory Settings; Default Settings; DMA Channel; Base I/O Address Selection
  • Page 21 – Table 2-2. Switch Settings with Corresponding Base I/O Address; Switch Setting
  • Page 22 – DMA Channel Selection; Each DMA channel consists of two signal lines as shown in Table 2-3.
  • Page 23 – Figure 2-4. DMA Jumper Settings for Disabling DMA Transfers; Interrupt Selection; most IBM PC and compatible computers.
  • Page 24 – Figure 2-6. Interrupt Jumper Setting for Disabling Interrupts; Analog I/O Configuration; Referenced single-ended input mode
  • Page 25 – Parameter; Analog Output Configuration; Bipolar Output Selection
  • Page 26 – Unipolar Output Selection; Analog Output Channel 0; Figure 2-8. Unipolar Output Jumper Configuration; Analog Input Configuration; Input Mode
  • Page 27 – Configuration; /D bit as described in the Command
  • Page 28 – This configuration is shown in Figure 2-9.; __ /D bit as described in the Command Register 4 bit description in
  • Page 29 – Analog Input Polarity Configuration; Bipolar Input Selection
  • Page 30 – Unipolar Input Selection; Analog Input
  • Page 31 – Hardware Installation; Remove the expansion slot cover on the back panel of the computer.
  • Page 32 – I/O Connector Pin Description; liable for any damages resulting from any such signal
  • Page 33 – Signal Connection Descriptions
  • Page 34 – Pin
  • Page 35 – Analog Input Signal Connections; liable for any damages resulting from
  • Page 36 – Types of Signal Sources; Floating Signal Sources
  • Page 37 – Ground-Referenced Signal Sources; Input Configurations; and Floating Signal Sources; Type of Signal; Floating; Differential Connection Considerations (DIFF Configuration)
  • Page 38 – Leads connecting the signals to the Lab-PC+ are greater than 15 ft.; Differential Connections for Grounded Signal Sources
  • Page 39 – Differential Connections for Floating Signal Sources
  • Page 40 – Figure 3-4. Differential Input Connections for Floating Sources
  • Page 41 – Single-Ended Connection Considerations
  • Page 43 – Common-Mode Signal Rejection Considerations
  • Page 44 – Digital I/O Signal Connections
  • Page 45 – Minimum
  • Page 46 – Port C Pin Connections
  • Page 47 – *Indicates that the signal is active low.
  • Page 48 – Name
  • Page 49 – Mode 1 Input Timing; All timing values are in nanoseconds.
  • Page 50 – Mode 1 Output Timing
  • Page 51 – Mode 2 Bidirectional Timing
  • Page 52 – Timing Connections; Data Acquisition Timing Connections
  • Page 53 – Figure 3-10. Posttrigger Data Acquisition Timing Case 1
  • Page 54 – Figure 3-12. Pretrigger Data Acquisition Timing
  • Page 55 – Figure 3-13. EXTUPDATE* Signal Timing for Updating DAC Output
  • Page 57 – Figure 3-16. Frequency Measurement Application
  • Page 59 – Cabling
  • Page 60 – Functional Overview
  • Page 61 – The following are the major components making up the Lab-PC+ board:; PC I/O Channel Interface Circuitry
  • Page 62 – When an A/D conversion is available to be read from FIFO
  • Page 63 – When a digital I/O port is ready to transfer data; Analog Input and Data Acquisition Circuitry
  • Page 64 – Analog Input Circuitry
  • Page 65 – Single-Channel Data Acquisition
  • Page 66 – Data Acquisition Rates; Table 4-1. Analog Input Settling Time Versus Gain; Gain Setting; s maximum
  • Page 67 – Single Channel
  • Page 68 – Analog Output Circuitry; Figure 4-4. Analog Output Circuitry Block Diagram
  • Page 69 – Digital I/O Circuitry
  • Page 74 – Calibration Equipment Requirements
  • Page 75 – Calibration Trimpots
  • Page 76 – Analog Input Calibration; Offset errors
  • Page 77 – Input Range
  • Page 78 – Unipolar Input Calibration Procedure; Input Offset Calibration
  • Page 79 – Analog Output Calibration; Analog output offset error
  • Page 81 – Unipolar Output Calibration Procedure; Adjust the Analog Output Gain; For analog output Channel 0:
  • Page 82 – Board Gain
  • Page 83 – in parallel with 45 pF; Gain; minutes
  • Page 84 – Explanation of Analog Input Specifications
  • Page 85 – Analog Output; Explanation of Analog Output Specifications
  • Page 86 – Level
  • Page 87 – Triggers; Digital Trigger; Bus Interface
  • Page 117 – Register Map
  • Page 118 – Register Name
  • Page 119 – Register Sizes; Register Description; Register Description Format
  • Page 120 – Configuration and Status Register Group
  • Page 121 – Command Register 1; Bit; SCANEN; Selected Gain
  • Page 122 – TWOSCMP
  • Page 123 – Status Register; EXTGATA0
  • Page 124 – OVERRUN
  • Page 125 – Command Register 2; TBSEL
  • Page 126 – SWTRIG
  • Page 127 – Command Register 3; FIFOINTEN
  • Page 128 – DIOINTEN
  • Page 129 – ECLKRCV
  • Page 130 – ECKDRV
  • Page 131 – Analog Input Register Group
  • Page 132 – Straight binary mode; High Byte
  • Page 134 – Not applicable, no bits used
  • Page 135 – Start Convert Register
  • Page 136 – DMATC Interrupt Clear Register
  • Page 137 – Analog Output Register Group
  • Page 138 – DACxL; DACxH
  • Page 139 – 253 Counter/Timer Register Groups A and B
  • Page 140 – Counter A0 Data Register
  • Page 141 – Counter A1 Data Register
  • Page 142 – Counter A2 Data Register
  • Page 143 – Counter A Mode Register
  • Page 144 – Timer Interrupt Clear Register
  • Page 145 – Counter B0 Data Register
  • Page 146 – Counter B1 Data Register
  • Page 147 – Counter B2 Data Register
  • Page 148 – Counter B Mode Register
  • Page 149 – 255A Digital I/O Register Group
  • Page 150 – Port A Register
  • Page 151 – Port B Register
  • Page 152 – Port C Register
  • Page 153 – Digital Control Register
  • Page 154 – Interval Counter Register Group
  • Page 155 – Interval Counter Data Register; Interval Counter count.
  • Page 156 – Interval Counter Strobe Register; Each of these bits must be 0 for proper operation of the Lab-PC+.
  • Page 157 – Register Programming Considerations
  • Page 158 – This sequence leaves the Lab-PC+ circuitry in the following state:; Programming the Analog Input Circuitry
  • Page 159 – Analog Input Circuitry Programming Sequence
  • Page 160 – used for A/D timing, the DAVAIL bit should be set after 12; A/D FIFO Output Binary Modes
  • Page 161 – Clearing the Analog Input Circuitry; Analog input error flags OVERFLOW and OVERRUN are cleared.
  • Page 162 – s must be observed for data integrity.; Programming in Controlled Acquisition Mode; example, programming a timebase of 10
  • Page 163 – s. N is referred to as the sample interval, that
  • Page 164 – Programming in Freerun Acquisition Mode
  • Page 166 – Start and service the data acquisition operation.
  • Page 168 – Using the EXTCONV* Signal to Initiate A/D Conversions; Posttrigger Mode
  • Page 169 – To program the counters, use the following programming sequence:
  • Page 170 – Pretrigger Mode; Select analog input channel and gain and select pretrigger mode.
  • Page 171 – To program the counters, use the following programming sequence.
  • Page 172 – Start and service the data acquisition operation.
  • Page 175 – Use a software trigger to initiate the operation.; A/D Interrupt Programming; Two different interrupts are generated by the A/D circuitry:
  • Page 176 – Programming DMA Operation; Register clears the DMATC bit in the Status Register.; Programming the Analog Output Circuitry
  • Page 177 – Table E-3. Analog Output Voltage Versus Digital Code; Digital Code
  • Page 178 – Table E-4. Analog Output Voltage Versus Digital Code; Interrupt Programming for the Analog Output Circuitry
  • Page 179 – Programming the Digital I/O Circuitry; Register Descriptions and Programming Examples
  • Page 181 – Modes of Operation for the 8255A; The three basic modes of operation for the 8255A are as follows:; Control Words
  • Page 183 – Input
  • Page 185 – Programming Example; Example 1. Configure Port A as an input port in Mode 1:; Output
  • Page 186 – INTEA
  • Page 187 – Example 1. Configure Port A as an output port in Mode 1:
  • Page 188 – IBFA
  • Page 190 – Single Bit Set/Reset Feature; Interrupt Programming for the Digital I/O Circuitry
  • Page 191 – Branch Offices
  • Page 192 – Technical Support Form
  • Page 194 – Documentation Comment Form
  • Page 195 – Glossary; Prefix
  • Page 197 – Index; Numbers
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© Copyright 1992, 1996 National Instruments Corporation.

All Rights Reserved.

Lab-PC+

User Manual

Low-Cost Multifunction I/O Board for ISA

June 1996 Edition

Part Number 320502B-01

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Summary

Page 5 - Contents; About This Manual; xi

© National Instruments Corporation v Lab-PC+ User Manual Contents About This Manual ........................................................................................................... xi Organization of the Lab-PC+ User Manual ....................................................................

Page 8 - Figures

Contents Lab-PC+ User Manual viii © National Instruments Corporation Figures Figure 1-1. The Relationship between the Programming Environment,NI-DAQ, and Your Hardware ............................................................................ 1-3 Figure 2-1. Parts Locator Diagram ....................

Page 9 - Tables

Contents © National Instruments Corporation ix Lab-PC+ User Manual Tables Table 2-1. PC Bus Interface Factory Settings ..................................................................... 2-3 Table 2-2. Switch Settings with Corresponding Base I/O Address andBase I/O Address Space .....................

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