Page 2 - NOTICE; © SEIKO EPSON CORPORATION 2001 All rights reserved.
NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of SeikoEpson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume anyliability of any kind arising out of any inaccuraci...
Page 3 - Devices; Specification; Development tools; Configuration of product number
S1C63 Family Devices S1 C 63158 F 0A01 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G : TCP BT 4 directions 0H : TCP BD 4 directions 0J : T...
Page 5 - ORE; CPU M; ANUAL; PREFACE
S1C63000 CORE CPU MANUAL EPSON i CONTENTS S1C63000 C ORE CPU M ANUAL PREFACE This manual explains the architecture, operation and instruction of the core CPU S1C63 of the CMOS 4-bitsingle chip microcomputer S1C63 Family.Also, since the memory configuration and the peripheral circuit configuration is...
Page 6 - EPSON
ii EPSON S1C63000 CORE CPU MANUAL CONTENTS 3.5 Interrupts ...................................................................................................... 26 3.5.1 Interrupt vectors ........................................................................................ 263.5.2 Interrupt seque...
Page 7 - Instruction Set Features
S1C63000 CORE CPU MANUAL EPSON 1 CHAPTER 1: OUTLINE CHAPTER 1 O UTLINE The S1C63000 is the core CPU of the 4-bit single chip microcomputer S1C63 Family that utilizes original EPSON architecture. It has a large and linear addressable space, maximum 64K words (13 bits/word) program memory (code ROM ar...
Page 10 - ALU and Registers
4 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE CHAPTER 2 A RCHITECTURE This chapter explains the S1C63000 ALU, registers, configuration of the program memory area and data memory area, and addressing. 2.1 ALU and Registers 2.1.1 ALU The ALU (Arithmetic and Logic Unit) loads 4-bit data from...
Page 11 - • A and B registers; Arithmetic instructions that change the Z flag:
S1C63000 CORE CPU MANUAL EPSON 5 CHAPTER 2: ARCHITECTURE • A and B registers The A and B registers are respective 4-bit data registers that are used for data transfer and operationwith other registers, data memories or immediate data. They are used independently for 4-bit trans-fer/operations and us...
Page 12 - Shift/Rotate instructions that change the Z flag:; • I flag
6 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE Shift/Rotate instructions that change the Z flag: SLL, SRL, RL, RR The Z flag is used for condition judgments when executing the conditional jump ("JRZ sign8" and"JRNZ sign8") instructions, thus it is possible to branch process...
Page 13 - Arithmetic operations with numbering system; The following shows examples of these operation.
S1C63000 CORE CPU MANUAL EPSON 7 CHAPTER 2: ARCHITECTURE 2.1.4 Arithmetic operations with numbering system In the S1C63000, some instructions support a numbering system. These instructions are indicated withthe following notations in the instruction list. ADC operand,n4 SBC operand,n4 INC operand,n4...
Page 14 - • Notes in numbering operations; • Data setting to the EXT register
8 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE • Notes in numbering operations When performing a numbering operation, set operands in correct notation according to the radixbefore operation.For example, if a decimal operation is done for hexadecimal values (AH to FH), the correct operation...
Page 15 - Reads all the flag data
S1C63000 CORE CPU MANUAL EPSON 9 CHAPTER 2: ARCHITECTURE The EXT register maintains the data set previously until new data is written or an initial reset. In otherwords, the content of the EXT register becomes valid by only setting the E flag using an above instruc-tion without the register writing ...
Page 16 - • 16-bit data transfer/arithmetic for the index registers X and Y
10 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE • 16-bit data transfer/arithmetic for the index registers X and Y The following six instructions, which handle the X or Y register and have an 8-bit immediate data asthe operand, permit the extended addressing. LDB %XL,imm8 LDB %YL,imm8 ADD %...
Page 17 - 3 bits) program memory space. In the individual
S1C63000 CORE CPU MANUAL EPSON 11 CHAPTER 2: ARCHITECTURE 2.2 Program Memory 2.2.1 Configuration of program memory The S1C63000 can access a maximum 64K-word ( × 13 bits) program memory space. In the individual model of the S1C63 Family, the ROM of which size is decided depending on the model is con...
Page 18 - Unconditional jump
12 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE 2.2.3 Branch instructions Various branch instructions are provided for program repeat and subroutine calls that change a sequen-tial program flow controlled with the PC. The branch instruction modifies the PC to branch the programto an option...
Page 19 - relative address
S1C63000 CORE CPU MANUAL EPSON 13 CHAPTER 2: ARCHITECTURE (2) Instruction with a 4-bit A register data that specifies a relative address JR %A This instruction branches the program sequence with the content of the A register as an unsigned4-bit relative address. The range that can be branched is fro...
Page 20 - CALR sign8
14 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE PC relative jump instructions Program memory 0000H FFFFH xxxxH xxxxH-127 JR sign8 xxxxH+128 0000H FFFFH xxxxH-1 xxxxH xxxxH-32767 LDB %EXT,imm8 JR sign8 xxxxH+32768 0000H FFFFH xxxxH JR %A xxxxH+16 A=0 → xxxxH+1 :A=15 → xxxxH+16 0000H FFFFH x...
Page 21 - LDB
S1C63000 CORE CPU MANUAL EPSON 15 CHAPTER 2: ARCHITECTURE This instruction permits the extended addressing with the E flag, and the 8-bit relative address canbe extended into 16 bits (the contents of the EXT register becomes the high-order 8 bits). In thiscase, the range that can be branched is from...
Page 23 - BCD to ASCII conversion
S1C63000 CORE CPU MANUAL EPSON 17 CHAPTER 2: ARCHITECTURE TOASCII: ;BCD to ASCII conversion LDB %EXT,0x00 ;Sets address 0040H LDB %XL,0x40 JR %A RETD 0x30 ;"0" RETD 0x31 ;"1" RETD 0x32 ;"2" RETD 0x33 ;"3" RETD 0x34 ;"4" RETD 0x35 ;"5" RETD 0x36 ;"6...
Page 24 - ...Loads the content of the memory address 0010H into the A register; • Accessing for addresses 0000H to 00FFH
18 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE 2.3.2 Addressing for data memory For addressing to access the data memory, the index registers X and Y, and stack pointers SP1 and SP2 areused. (The next section will explain the stack pointers.) Index registers X and Y are both 16-bit regist...
Page 25 - CLR; Stack pointer 1
S1C63000 CORE CPU MANUAL EPSON 19 CHAPTER 2: ARCHITECTURE • Accessing for addresses 0000H to 003FH Data in this area is used for a relative address by the "JR [addr6]" and "CALR [addr6]" explained inSection 2.2.3. This area is suitable for setting up various flags and counters since ...
Page 26 - • Queue register
20 EPSON S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE The SP1 increment/decrement affects only the 8-bit field shown in Figure 2.3.3.1, and its operation isperformed cyclically. In other words, if the SP1 is decremented by the PUSH instruction or otherconditions when the SP1 is 00H (indicating t...
Page 28 - CPU O; PERATION; Timing Generator and Bus Cycle; Instruction Fetch and Execution
22 EPSON S1C63000 CORE CPU MANUAL CHAPTER 3: CPU OPERATION CHAPTER 3 CPU O PERATION This section explains the CPU operations and the operation timings. 3.1 Timing Generator and Bus Cycle The S1C63000 has a built-in timing generator. The timing generator of the S1C63000 generates the two-phase divide...
Page 29 - The data bus goes to a high-impedance during an execution cycle (
S1C63000 CORE CPU MANUAL EPSON 23 CHAPTER 3: CPU OPERATION 3.3 Data Bus (Data Memory) Control 3.3.1 Data bus status The S1C63000 output the data bus status in each bus cycle externally on the DBS0 and DBS1 signals as a2-bit status. The peripheral circuits perform the direction control of the bus dri...
Page 32 - Initial setting of internal registers; NMI interrupt vector:
26 EPSON S1C63000 CORE CPU MANUAL CHAPTER 3: CPU OPERATION After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 andSP2 are set by software. 3.4.2 Initial setting of internal registers An initial reset initializes the internal registers in the CPU as s...
Page 33 - • Hardware interrupts; • Exceptional acceptance of interrupt
S1C63000 CORE CPU MANUAL EPSON 27 CHAPTER 3: CPU OPERATION Each of the addresses listed above corresponds to an interrupt factor individually. A branch (jump)instruction to the interrupt service routine should be written to these addresses. Up to 15 hardware interrupt vectors are available, however,...
Page 34 - Instructions that set the stack pointer
28 EPSON S1C63000 CORE CPU MANUAL CHAPTER 3: CPU OPERATION 3. Instructions that set the stack pointer LDB %SP1,%BA LDB %SP2,%BA These two instructions are also accepted after fetching the next instruction. However, theseinstructions must be executed as a pair. When one of them is fetched at first, a...
Page 36 - • Software interrupts
30 EPSON S1C63000 CORE CPU MANUAL CHAPTER 3: CPU OPERATION • Software interrupts The software interrupts are generated by the INT instruction. Time of the interrupt generation isdetermined by the software, so the I flag setting does not affect the interrupt. That processing is thesame as the subrout...
Page 39 - • Types of addressing modes
S1C63000 CORE CPU MANUAL EPSON 33 CHAPTER 4: INSTRUCTION SET CHAPTER 4 I NSTRUCTION S ET The S1C63000 offers high machine cycle efficiency and a high speed instruction set. It has 47 basic instructions (412 instructions in all) that are designed as an instruction system permitting relocatableprogram...
Page 40 - • Register direct addressing
34 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET • Register direct addressing The register direct addressing is the addressing mode when specifying a register for the source and/or destination. Register names should be written with % in front.Instructions in which the operand has the fol...
Page 41 - (2) Instructions that access from FFC0H to FFFFH; • Signed 8-bit PC relative addressing
S1C63000 CORE CPU MANUAL EPSON 35 CHAPTER 4: INSTRUCTION SET These instructions perform a PC relative branch using the content (4 bits) of a memory specifiedwith the [addr6] as a relative address. The branch destination address is [the address next to thebranch instruction] + [the contents (0 to 15)...
Page 42 - • 8-bit absolute addressing; Instruction
36 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET Examples: LDB %EXT,0x15 LDB %XL,0x7D ...Works as "LD %X, 0157D" LDB %EXT,0xB8 ADD %X,0x4F ...Works as "ADD %X, 0xB84F" LDB %EXT,0xE6 CMP %X,0xA2 ...Works as "CMP %X, 0x19A2" ∗ 19H = FFH - [EXT] (E6H) Above examples ...
Page 43 - • Signed 16-bit PC relative addressing
S1C63000 CORE CPU MANUAL EPSON 37 CHAPTER 4: INSTRUCTION SET • Signed 16-bit PC relative addressing The addressing mode of the following branch instructions, which have an 8-bit relative address as theoperand, change to the signed 16-bit PC relative addressing with the E flag set to "1". Con...
Page 44 - Register names
38 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET 4.2.2 Symbol meanings The following indicates the meanings of the symbols used in the instruction list. Register names A ........................... Data register A (4 bits)B ........................... Data register B (4 bits)BA ............
Page 45 - Memory
S1C63000 CORE CPU MANUAL EPSON 39 CHAPTER 4: INSTRUCTION SET Memory [%X], [X] ............. Memory where the X register specifies[%Y], [Y] ............. Memory where the Y register specifies[00addr6] ............ Memory within 0000H to 003FH where the addr6 specifies[FFaddr6] ............ Memory wit...
Page 52 - ALU shift and rotate operation
46 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SLL %A %B [%X] [%X]+ [%Y] [%Y]+ SRL %A %B [%X] [%X]+ [%Y] [%Y]+ RL %A %B [%X] [%X]+ [%Y] [%Y]+ RR %A %B [%X] [%X]+ [%Y] [%Y]+ 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0...
Page 53 - cated with; Branch control; System control
S1C63000 CORE CPU MANUAL EPSON 47 CHAPTER 4: INSTRUCTION SET Note: • The extended addressing (combined with the E flag) is available only for the instructions indi- cated with ● ● in the EXT. mode row. Operation of other instructions (indicated with × ) cannot be guaranteed, therefore do not write d...
Page 61 - List of extended addressing instructions
S1C63000 CORE CPU MANUAL EPSON 55 CHAPTER 4: INSTRUCTION SET 4.2.5 List of extended addressing instructions ↓ – – – ↓ – – – ↓ – – – ↓ – – – ↓ – – – ↓ – – – ↓ – – – ↓ – – – ↓ – – – ↓ – – – ↓ – – – ↓ – – – ↓ – – – ↓ – – – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – ↓ – A ← [00imm8]...
Page 65 - Instruction Formats; II
S1C63000 CORE CPU MANUAL EPSON 59 CHAPTER 4: INSTRUCTION SET 4.3 Instruction Formats All the instructions of the S1C63000 are configured with 1 word (13 bits) as follows: I OP Code Examples: LDADDPUSH %A,%B%A,[%X]%F II OP Code Examples: LDADCBIT %A,imm4[%Y],%B,n4%B,imm4 III OP Code Examples: INCCALR...
Page 66 - Detailed Explanation of Instructions; View of the explanation
60 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET Add with carry r' reg. to r reg. 1 cycle Function: r ← r + r' + C Adds the content of the r' register (A or B) and carry (C) to the r register (A or B). Code: Mnemonic MSB LSB ADC %A,%A 1 1 0 0 1 1 1 1 1 0 0 0 X 19F0H, (19F1H) ADC %A,%B 1 ...
Page 67 - Add with carry immediate data imm4 to r reg.
S1C63000 CORE CPU MANUAL EPSON 61 CHAPTER 4: INSTRUCTION SET ADC %r,%r' ADC %r,imm4 Add with carry immediate data imm4 to r reg. 1 cycle Function: r ← r + imm4 + C Adds the 4-bit immediate data imm4 and carry (C) to the r register (A or B). Code: Mnemonic MSB LSB ADC %A,imm4 1 1 0 0 1 1 1 0 0 i3 i2 ...
Page 68 - Extended
62 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET ADC %r,[%ir] Add with carry location [ir reg.] to r reg. 1 cycle Function: r ← r + [ir] + C Adds the content of the data memory addressed by the ir register (X or Y) and carry (C) to the rregister (A or B). Code: Mnemonic MSB LSB ADC %A,[%...
Page 69 - cycles
S1C63000 CORE CPU MANUAL EPSON 63 CHAPTER 4: INSTRUCTION SET ADC [%ir],%r Add with carry r reg. to location [ir reg.] 2 cycles Function: [ir] ← [ir] + r + C Adds the content of the r register (A or B) and carry (C) to the data memory addressed by the irregister (X or Y). Code: Mnemonic MSB LSB ADC [...
Page 71 - Add with carry A reg. to B reg. in specified radix; n4 should be specified with a value from 1 to 16.
S1C63000 CORE CPU MANUAL EPSON 65 CHAPTER 4: INSTRUCTION SET ADC %B,%A,n4 Add with carry A reg. to B reg. in specified radix 2 cycles Function: B ← N's adjust (B + A + C) Adds the content of the A register and carry (C) to the B register. The operation result isadjusted with n4 as the radix. The C f...
Page 75 - Add immediate data imm4 to r reg.
S1C63000 CORE CPU MANUAL EPSON 69 CHAPTER 4: INSTRUCTION SET ADD %r,imm4 Add immediate data imm4 to r reg. 1 cycle Function: r ← r + imm4 Adds the 4-bit immediate data imm4 to the r register (A or B). Code: Mnemonic MSB LSB ADD %A,imm4 1 1 0 0 1 0 1 0 0 i3 i2 i1 i0 1940H–194FH ADD %B,imm4 1 1 0 0 1 ...
Page 78 - ir
72 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET ADD [%ir]+,imm4 Add immediate data imm4 to location [ir reg.] and increment ir reg. 2 cycles Function: [ir] ← [ir] + imm4, ir ← ir + 1 Adds the 4-bit immediate data imm4 to the data memory addressed by the ir register (X or Y).Then increme...
Page 79 - Add immediate data sign8 to ir reg.
S1C63000 CORE CPU MANUAL EPSON 73 CHAPTER 4: INSTRUCTION SET ADD %ir,sign8 Add immediate data sign8 to ir reg. 1 cycle Function: ir ← ir + sign8 Adds the signed 8-bit immediate data sign8 (-128 to 127) to the ir register (X or Y). This instruc-tion does not affect the C flag regardless of the operat...
Page 80 - Logical AND of immediate data imm4 and r reg.
74 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET AND %r,imm4 Logical AND of immediate data imm4 and r reg. 1 cycle Function: r ← r ∧ imm4 Performs a logical AND operation of the 4-bit immediate data imm4 and the content of the rregister (A or B), and stores the result in the r register. ...
Page 88 - Call subroutine at relative location [addr6]; Call subroutine at relative location sign8
82 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET CALR [addr6] Call subroutine at relative location [addr6] 2 cycles Function: ([(SP1-1) * 4+3]~[(SP1-1) * 4]) ← PC + 1, SP1 ← SP1 - 1, PC ← PC + [addr6] + 1 (addr6 = 0000H–003FH)Saves the address next to this instruction to the stack as a r...
Page 89 - Call subroutine at location imm8; CALZ imm8
S1C63000 CORE CPU MANUAL EPSON 83 CHAPTER 4: INSTRUCTION SET CALZ imm8 Call subroutine at location imm8 1 cycle Function: ([(SP1-1) * 4+3]~[(SP1-1) * 4]) ← PC + 1, SP1 ← SP1 - 1, PC ← imm8 Saves the address next to this instruction to the stack as a return address, then unconditionallycalls the subr...
Page 90 - Compare r reg. with immediate data imm4
84 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET CMP %r,%r’ CMP %r,imm4 Compare r reg. with immediate data imm4 1 cycle Function: r - imm4Subtracts the 4-bit immediate data imm4 from the content of the r register (A or B). It changesthe flags (Z and C), but does not change the content of...
Page 94 - Compare ir reg. with immediate data imm8
88 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET CMP %ir,imm8 DEC [addr6] Compare ir reg. with immediate data imm8 1 cycle Function: ir - imm8Subtracts the 8-bit immediate data imm8 from the content of the ir register (X or Y). It changesthe flags (Z and C), but does not change the regis...
Page 95 - Decrement location [ir] in specified radix; Decrement location [ir] in specified radix and increment ir reg.
S1C63000 CORE CPU MANUAL EPSON 89 CHAPTER 4: INSTRUCTION SET DEC [ir],n4 Decrement location [ir] in specified radix 2 cycles Function: [ir] ← N’s adjust ([ir] - 1) Decrements (-1) the content of the data memory addressed by the ir register (X or Y). Theoperation result is adjusted with n4 as the rad...
Page 96 - Exchanges the contents of the A register and B register.; Decrement stack pointer; sp
90 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET DEC %sp EX %A,%B Exchange A reg. and B reg. 1 cycle Function: A ↔ B Exchanges the contents of the A register and B register. Code: Mnemonic MSB LSB EX %A,%B 1 1 1 1 1 1 1 1 1 0 1 1 1 1FF7H Flags: E I C Z ↓ – – – Mode: Src: Register directD...
Page 98 - Set CPU to HALT mode; HALT
92 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET HALT Set CPU to HALT mode 2 cycles Function: HaltSets the CPU to HALT status.The CPU stops operating, thus the power consumption is reduced. Peripheral circuits such asthe oscillation circuit still operate.An interrupt causes it to return ...
Page 99 - Increment location [ir] in specified radix; Increment location [ir] in specified radix and increment ir reg.
S1C63000 CORE CPU MANUAL EPSON 93 CHAPTER 4: INSTRUCTION SET INC [ir],n4 Increment location [ir] in specified radix 2 cycles Function: [ir] ← N’s adjust ([ir] + 1) Increments (+1) the content of the data memory addressed by the ir register (X or Y). Theoperation result is adjusted with n4 as the rad...
Page 100 - Software interrupt; INT imm6; Increment stack pointer
94 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET INC %sp INT imm6 Software interrupt 3 cycles Function: [SP2-1] ← F, SP2 ← SP2 - 1, ([(SP1-1) * 4+3]~[(SP1-1) * 4]) ← PC + 1, SP1 ← SP1 - 1, PC ← imm6 (imm6 = 0100H–013FH)Saves the content of the F register and the return address (this inst...
Page 101 - Indirect jump using Y reg.; Jump to relative location A reg.; PC
S1C63000 CORE CPU MANUAL EPSON 95 CHAPTER 4: INSTRUCTION SET JP %Y Indirect jump using Y reg. 1 cycle Function: PC ← Y Loads the content of the Y register into the PC to branch unconditionally. Code: Mnemonic MSB LSB JP %Y 1 1 1 1 1 1 1 1 1 0 0 1 X 1FF2H, (1FF3H) Flags: E I C Z ↓ – – – Mode: Registe...
Page 102 - Jump to relative location BA reg.
96 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET JR %BA Jump to relative location BA reg. 1 cycle Function: PC ← PC + BA + 1 Adds the content of the BA register to the address next to this instruction, to unconditionallybranch to that address. Branch destination range is the next address...
Page 103 - JR sign8; Jump to relative location sign8; JRC sign8; Jump to relative location sign8 if C flag is set
S1C63000 CORE CPU MANUAL EPSON 97 CHAPTER 4: INSTRUCTION SET JR sign8 Jump to relative location sign8 1 cycle Function: PC ← PC + sign8 + 1 (sign8 = -128~127) Adds the relative address specified with the sign8 to the address next to this instruction, tounconditionally branch to that address. Branch ...
Page 104 - JRNC sign8; Jump to relative location sign8 if C flag is reset; JRNZ sign8; Jump to relative location sign8 if Z flag is reset
98 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET JRNC sign8 Jump to relative location sign8 if C flag is reset 1 cycle Function: If C = 0 then PC ← PC + sign8 + 1 (sign8 = -128~127) Executes the "JR sign8" instruction if the C (carry) flag has been reset to "0", otherwise...
Page 105 - Jump to relative location sign8 if Z flag is set; JRZ sign8
S1C63000 CORE CPU MANUAL EPSON 99 CHAPTER 4: INSTRUCTION SET JRZ sign8 Jump to relative location sign8 if Z flag is set 1 cycle Function: If Z = 1 then PC ← PC + sign8 + 1 (sign8 = -128~127) Executes the "JR sign8" instruction if the Z (zero) flag has been reset to "0", otherwise exe...
Page 106 - Load immediate data imm4 into r reg.
100 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET LD %r,imm4 Load immediate data imm4 into r reg. 1 cycle Function: r ← imm4 Loads the 4-bit immediate data imm4 into the r register (A, B or F). Code: Mnemonic MSB LSB LD %A,imm4 1 1 1 1 0 1 1 0 0 i3 i2 i1 i0 1EC0H–1ECFH LD %B,imm4 1 1 1 1...
Page 111 - Load immediate data imm8 into BA reg.; BA
S1C63000 CORE CPU MANUAL EPSON 105 CHAPTER 4: INSTRUCTION SET LD [%ir]+,[%ir’]+ Load location [ir’ reg.] into location [ir reg.] and increment ir and ir’ reg. 2 cycles Function: [ir] ← [ir ’], ir ← ir + 1, ir ’ ← ir ’ + 1 Loads the content of the data memory addressed by the ir ’ register (X or Y) i...
Page 113 - Load stack pointer into BA reg.
S1C63000 CORE CPU MANUAL EPSON 107 CHAPTER 4: INSTRUCTION SET LDB %BA,%rr Load rr reg. into BA reg. 1 cycle Function: BA ← rr Loads the content of the rr register (XL, XH, YL or YH) into the BA register. Code: Mnemonic MSB LSB LDB %BA,%XL 1 1 1 1 1 1 1 0 0 1 0 0 0 1FC8H LDB %BA,%XH 1 1 1 1 1 1 1 0 0...
Page 115 - Load immediate data imm8 into EXT reg.; EXT
S1C63000 CORE CPU MANUAL EPSON 109 CHAPTER 4: INSTRUCTION SET LDB %EXT,imm8 Load immediate data imm8 into EXT reg. 1 cycle Function: EXT ← imm8 Loads the 8-bit immediate data into the EXT register. The E flag is set to "1". Code: Mnemonic MSB LSB LDB %EXT,imm8 0 1 0 0 0 i7 i6 i5 i4 i3 i2 i1 ...
Page 116 - Load immediate data imm8 into rr reg.; rr
110 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET LDB %rr,imm8 Load immediate data imm8 into rr reg. 1 cycle Function: rr ← imm8 Loads the 8-bit immediate data imm8 into the rr (XL or YL) register. Code: Mnemonic MSB LSB LDB %XL,imm8 0 1 0 1 0 i7 i6 i5 i4 i3 i2 i1 i0 0A00H–0AFFH LDB %YL,...
Page 117 - Load BA reg. into stack pointer; No operation; NOP
S1C63000 CORE CPU MANUAL EPSON 111 CHAPTER 4: INSTRUCTION SET LDB %sp,%BA Load BA reg. into stack pointer 1 cycle Function: sp ← BA Loads the content of the BA register into the stack pointer sp (SP1 or SP2). Code: Mnemonic MSB LSB LDB %SP1,%BA 1 1 1 1 1 1 1 0 0 0 1 0 X 1FC4H, (1FC5H) LDB %SP2,%BA 1...
Page 119 - Logical OR of immediate data imm4 and F reg.
S1C63000 CORE CPU MANUAL EPSON 113 CHAPTER 4: INSTRUCTION SET OR %F,imm4 Logical OR of immediate data imm4 and F reg. 1 cycle Function: F ← F ∨ imm4 Performs a logical OR operation of the 4-bit immediate data imm4 and the content of the F(flag) register, and stores the result in the r register. It i...
Page 122 - Pop top of stack into r reg.
116 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET OR [%ir]+,imm4 Logical OR of immediate data imm4 and location [ir reg.] and increment ir reg. 2 cycles Function: [ir] ← [ir] ∨ imm4, ir ← ir +1 Performs a logical OR operation of the 4-bit immediate data imm4 and the content of the datame...
Page 123 - Push r reg. onto stack
S1C63000 CORE CPU MANUAL EPSON 117 CHAPTER 4: INSTRUCTION SET POP %ir PUSH %r Push r reg. onto stack 1 cycle Function: [SP2-1] ← r, SP2 ← SP2 -1 Decrements the stack pointer SP2, then stores the content of the r register (A, B or F) into theaddress indicated by the SP2. Code: Mnemonic MSB LSB PUSH %...
Page 124 - Push ir reg. onto stack; RET; Return from subroutine
118 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET PUSH %ir Push ir reg. onto stack 1 cycle Function: ([(SP1-1) * 4+3]~[(SP1-1) * 4]) ← ir, SP1 ← SP1 -1 Decrements the stack pointer SP1, then stores the content of the ir register (X or Y) into theaddresses (4 words) indicated by the SP1 (...
Page 125 - RETD imm8; Return from subroutine and load imm8 into location [X]; RETI; Return from interrupt routine
S1C63000 CORE CPU MANUAL EPSON 119 CHAPTER 4: INSTRUCTION SET RETD imm8 Return from subroutine and load imm8 into location [X] 3 cycles Function: PC ← ([SP1 * 4+3]~[SP1 * 4]), SP1 ← SP1 +1, [X] ← i3-0, [X+1] ← i7-4, X ← X + 2 After executing the RET instruction, stores the 8-bit immediate data imm8 ...
Page 126 - RETS; Rotate left r reg. with carry
120 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET RETS RL %r Rotate left r reg. with carry 1 cycle Function: Rotates the content of the r register (A or B) including the carry (C) to the left for 1 bit. Thecontent of the C flag moves to bit 0 of the r register and bit 3 moves to the C fl...
Page 128 - Rotate right r reg. with carry
122 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET RR %r RR [%ir] Rotate right r reg. with carry 1 cycle Function: Rotates the content of the r register (A or B) including the carry (C) to the right for 1 bit. Thecontent of the C flag moves to bit 3 of the r register and bit 0 moves to th...
Page 130 - Subtract with carry immediate data imm4 from r reg.
124 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SBC %r,imm4 Subtract with carry immediate data imm4 from r reg. 1 cycle Function: r ← r - imm4 - C Subtracts the 4-bit immediate data imm4 and carry (C) from the r register (A or B). Code: Mnemonic MSB LSB SBC %A,imm4 1 1 0 0 0 1 1 0 0 i3...
Page 132 - Subtract with carry immediate data imm4 from location [ir reg.]
126 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET SBC [%ir]+,%r Subtract with carry r reg. from location [ir reg.] and increment ir reg. 2 cycles Function: [ir] ← [ir] - r - C, ir ← ir + 1 Subtracts the content of the r register (A or B) and carry (C) from the data memory addressedby the...
Page 133 - Subtract with carry A reg. from B reg. in specified radix
S1C63000 CORE CPU MANUAL EPSON 127 CHAPTER 4: INSTRUCTION SET SBC [%ir]+,imm4 Subtract with carry immediate data imm4 from location [ir reg.] and increment ir reg. 2 cycles Function: [ir] ← [ir] - imm4 - C, ir ← ir + 1 Subtracts the immediate data imm4 and carry (C) from the data memory addressed by...
Page 139 - Set CPU to SLEEP mode; SLP; Shift right r reg. logical
S1C63000 CORE CPU MANUAL EPSON 133 CHAPTER 4: INSTRUCTION SET SLP Set CPU to SLEEP mode 2 cycles Function: SleepSets the CPU to SLEEP status.The CPU and the peripheral circuits including the oscillation circuit stops operating, thus thepower consumption is substantially reduced.An interrupt from out...
Page 146 - Exclusive OR immediate data imm4 and r reg.
140 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET XOR %r,imm4 Exclusive OR immediate data imm4 and r reg. 1 cycle Function: r ← r ∀ imm4 Performs an exclusive OR operation of the 4-bit immediate data imm4 and the content of the rregister (A or B), and stores the result in the r register....
Page 150 - Index
144 EPSON S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET Index ADC %r,%r’ ............ 61 ADC %r,imm4 ........ 61 ADC %r,[%ir] .......... 62 ADC %r,[%ir]+ ........ 62 ADC [%ir],%r .......... 63 ADC [%ir]+,%r ....... 63 ADC [%ir],imm4 ..... 64 ADC [%ir]+,imm4 ... 64 ADC %B,%A,n4 ..... 65 ADC %B,...
Page 151 - International Sales Operations
AMERICA EPSON ELECTRONICS AMERICA, INC. - HEADQUARTERS - 150 River Oaks ParkwaySan Jose, CA 95134, U.S.A.Phone: +1-408-922-0200 Fax: +1-408-922-0238 - SALES OFFICES - West 1960 E. Grand AvenueEI Segundo, CA 90245, U.S.A.Phone: +1-310-955-5300 Fax: +1-310-955-5400 Central 101 Virginia Street, Suite 2...
Page 152 - Core CPU Manual
EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION First issue July, 1995 Printed February, 2001 in Japan A M http://www.epsondevice.com Core CPU Manual S1C63000
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