Epson S1C63000- User Manual

Epson S1C63000

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Table of Contents:

  • Page 2 – NOTICE; © SEIKO EPSON CORPORATION 2001 All rights reserved.
  • Page 3 – Devices; Specification; Development tools; Configuration of product number
  • Page 5 – ORE; CPU M; ANUAL; PREFACE
  • Page 6 – EPSON
  • Page 7 – Instruction Set Features
  • Page 10 – ALU and Registers
  • Page 11 – • A and B registers; Arithmetic instructions that change the Z flag:
  • Page 12 – Shift/Rotate instructions that change the Z flag:; • I flag
  • Page 13 – Arithmetic operations with numbering system; The following shows examples of these operation.
  • Page 14 – • Notes in numbering operations; • Data setting to the EXT register
  • Page 15 – Reads all the flag data
  • Page 16 – • 16-bit data transfer/arithmetic for the index registers X and Y
  • Page 17 – 3 bits) program memory space. In the individual
  • Page 18 – Unconditional jump
  • Page 19 – relative address
  • Page 20 – CALR sign8
  • Page 21 – LDB
  • Page 23 – BCD to ASCII conversion
  • Page 24 – ...Loads the content of the memory address 0010H into the A register; • Accessing for addresses 0000H to 00FFH
  • Page 25 – CLR; Stack pointer 1
  • Page 26 – • Queue register
  • Page 28 – CPU O; PERATION; Timing Generator and Bus Cycle; Instruction Fetch and Execution
  • Page 29 – The data bus goes to a high-impedance during an execution cycle (
  • Page 32 – Initial setting of internal registers; NMI interrupt vector:
  • Page 33 – • Hardware interrupts; • Exceptional acceptance of interrupt
  • Page 34 – Instructions that set the stack pointer
  • Page 36 – • Software interrupts
  • Page 39 – • Types of addressing modes
  • Page 40 – • Register direct addressing
  • Page 41 – (2) Instructions that access from FFC0H to FFFFH; • Signed 8-bit PC relative addressing
  • Page 42 – • 8-bit absolute addressing; Instruction
  • Page 43 – • Signed 16-bit PC relative addressing
  • Page 44 – Register names
  • Page 45 – Memory
  • Page 52 – ALU shift and rotate operation
  • Page 53 – cated with; Branch control; System control
  • Page 61 – List of extended addressing instructions
  • Page 65 – Instruction Formats; II
  • Page 66 – Detailed Explanation of Instructions; View of the explanation
  • Page 67 – Add with carry immediate data imm4 to r reg.
  • Page 68 – Extended
  • Page 69 – cycles
  • Page 71 – Add with carry A reg. to B reg. in specified radix; n4 should be specified with a value from 1 to 16.
  • Page 75 – Add immediate data imm4 to r reg.
  • Page 78 – ir
  • Page 79 – Add immediate data sign8 to ir reg.
  • Page 80 – Logical AND of immediate data imm4 and r reg.
  • Page 88 – Call subroutine at relative location [addr6]; Call subroutine at relative location sign8
  • Page 89 – Call subroutine at location imm8; CALZ imm8
  • Page 90 – Compare r reg. with immediate data imm4
  • Page 94 – Compare ir reg. with immediate data imm8
  • Page 95 – Decrement location [ir] in specified radix; Decrement location [ir] in specified radix and increment ir reg.
  • Page 96 – Exchanges the contents of the A register and B register.; Decrement stack pointer; sp
  • Page 98 – Set CPU to HALT mode; HALT
  • Page 99 – Increment location [ir] in specified radix; Increment location [ir] in specified radix and increment ir reg.
  • Page 100 – Software interrupt; INT imm6; Increment stack pointer
  • Page 101 – Indirect jump using Y reg.; Jump to relative location A reg.; PC
  • Page 102 – Jump to relative location BA reg.
  • Page 103 – JR sign8; Jump to relative location sign8; JRC sign8; Jump to relative location sign8 if C flag is set
  • Page 104 – JRNC sign8; Jump to relative location sign8 if C flag is reset; JRNZ sign8; Jump to relative location sign8 if Z flag is reset
  • Page 105 – Jump to relative location sign8 if Z flag is set; JRZ sign8
  • Page 106 – Load immediate data imm4 into r reg.
  • Page 111 – Load immediate data imm8 into BA reg.; BA
  • Page 113 – Load stack pointer into BA reg.
  • Page 115 – Load immediate data imm8 into EXT reg.; EXT
  • Page 116 – Load immediate data imm8 into rr reg.; rr
  • Page 117 – Load BA reg. into stack pointer; No operation; NOP
  • Page 119 – Logical OR of immediate data imm4 and F reg.
  • Page 122 – Pop top of stack into r reg.
  • Page 123 – Push r reg. onto stack
  • Page 124 – Push ir reg. onto stack; RET; Return from subroutine
  • Page 125 – RETD imm8; Return from subroutine and load imm8 into location [X]; RETI; Return from interrupt routine
  • Page 126 – RETS; Rotate left r reg. with carry
  • Page 128 – Rotate right r reg. with carry
  • Page 130 – Subtract with carry immediate data imm4 from r reg.
  • Page 132 – Subtract with carry immediate data imm4 from location [ir reg.]
  • Page 133 – Subtract with carry A reg. from B reg. in specified radix
  • Page 139 – Set CPU to SLEEP mode; SLP; Shift right r reg. logical
  • Page 146 – Exclusive OR immediate data imm4 and r reg.
  • Page 150 – Index
  • Page 151 – International Sales Operations
  • Page 152 – Core CPU Manual
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Core CPU Manual

CMOS 4-BIT SINGLE CHIP MICROCOMPUTER

S1C63000

MF855-03a

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Summary

Page 2 - NOTICE; © SEIKO EPSON CORPORATION 2001 All rights reserved.

NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of SeikoEpson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume anyliability of any kind arising out of any inaccuraci...

Page 3 - Devices; Specification; Development tools; Configuration of product number

S1C63 Family Devices S1 C 63158 F 0A01 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G : TCP BT 4 directions 0H : TCP BD 4 directions 0J : T...

Page 5 - ORE; CPU M; ANUAL; PREFACE

S1C63000 CORE CPU MANUAL EPSON i CONTENTS S1C63000 C ORE CPU M ANUAL PREFACE This manual explains the architecture, operation and instruction of the core CPU S1C63 of the CMOS 4-bitsingle chip microcomputer S1C63 Family.Also, since the memory configuration and the peripheral circuit configuration is...

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