Epson P-0082- Manuals

Page 2 - Asynchronous Memory Access Cycles; ARDY; Host Bus Interface Pin Mapping; CLKOUT BUSCLK; Host Bus Interface Signal Descriptions; BUSCLK

a This section provides an overview of the operation of the CPU bus in order to establish interface requirements. Asynchronous Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus ( ADD[2:25] , /ABE3 ), the LCD chip select ( /CS ) is driven low by /AM...

Page 3 - Hardware Description; S1D13806 Hardware Functional Specification; Name; = BUSCLK input not divided

a address ( ADDR[2:20] , /ABE3 ) and data bus ( DATA[0:15] ), respectively. CONF[3:0] must be set to select the Generic Host Bus Interface with little endian mode. • M/R (memory/register) selects between memory or register access. It may be connected to an address line, allowing system address ADDR2...

Page 4 - Register/Memory Mapping; Memory Bank; BFF FFFF; Physical; X x

a Interfacing EPSON S1D13806 memory display controller to Blackfin® Processors (EE-184) Page 4 of 13 Figure 2: Typical Implementation of ADSP-BF535 to S1D13806 Interface Register/Memory Mapping The ADSP-BF535 supports four asynchronous memory regions. Each has a unique memory select ( AMS[x] ) assoc...

Page 5 - ADSP-BF535 Configuration; Software; R e f e r e n c e s; Hardware Functional Specification

a A typical implementation as shown in the schematic has the Memory/Register select pin ( M/R ) connected to ADSP-BF535 address line ADD21 . ADD21 selects between the S1D13806 display buffer ( ADD21=1 ) and internal registers ( ADD21=0 ). This implementation decodes as shown in the Table 4. Note: Th...

Page 6 - S o u r c e C o d e; #define S1D_REGDELAYOFF 0xFFFE

a S o u r c e C o d e //---------------------------------------------------------------------------- // // File generated by S1D13806CFG.EXE // // Copyright (c) 2000,2001 Epson Research and Development, Inc. // All rights reserved. // // PLEASE NOTE: If you FTP this file to a non-Windows platform, m...

Page 7 - typedef struct

a ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(b); \ } #define S1D_READ_PALETTE(p,i,r,g,b) \ { \ ((volatile S1D_VALUE*)(p))[0x1E2/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ r = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)]; \ g = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VAL...

Page 10 - //first address of the display buffer memory

a {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register {0x01FC,0x02}, // Display Mode Register }; Listing 1: Header file generated by the S1D13806CFG.EXE (EPSON) /////////////////////////////////////////////////////////////////////////////// // // FILE: S1D13806.c // // Analog Devices Inc....

Page 11 - // set Asynchronous Memory Control Registers

a void S1D13806_plot_hline(unsigned short x1,unsigned short y1,unsigned short x2,unsigned short color); void S1D13806_plot_vline(unsigned short x1,unsigned short y1,unsigned short y2,unsigned short color); /////////////////////////////////////////////////////////////////////////////// // void main()...

Page 13 - unsigned short temp; D o c u m e n t H i s t o r y; Version

a while(x1 <= x2) S1D13806_plot_xy(x1++, y1,color); } //Vertical line running down /* * x1,y2 * | * | * x1,y1 */ void S1D13806_plot_vline(unsigned short x1,unsigned short y1,unsigned short y2,unsigned short color) { unsigned short temp; if (y1 > y2){ //SWOP temp = y1; y1 = y2; y2 = temp; } whi...