Epson P-0082- User Manual
Epson P-0082– User Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Asynchronous Memory Access Cycles; ARDY; Host Bus Interface Pin Mapping; CLKOUT BUSCLK; Host Bus Interface Signal Descriptions; BUSCLK
- Page 3 – Hardware Description; S1D13806 Hardware Functional Specification; Name; = BUSCLK input not divided
- Page 4 – Register/Memory Mapping; Memory Bank; BFF FFFF; Physical; X x
- Page 5 – ADSP-BF535 Configuration; Software; R e f e r e n c e s; Hardware Functional Specification
- Page 6 – S o u r c e C o d e; #define S1D_REGDELAYOFF 0xFFFE
- Page 7 – typedef struct
- Page 10 – //first address of the display buffer memory
- Page 11 – // set Asynchronous Memory Control Registers
- Page 13 – unsigned short temp; D o c u m e n t H i s t o r y; Version
Engineer To Engineer Note
EE-184
a
Technical Notes on using Analog Devices' DSP components and development tools
Contact our technical support by phone: (800) ANALOG-D or e-mail: [email protected]
Or visit our on-line resources http://www.analog.com/dsp and http://www.analog.com/dsp/EZAnswers
Interfacing EPSON S1D13806 memory display controller to Blackfin®
Processors
Contributed by Michael Hennerich
May 20, 2003
I n t r o d u c t i o n
The Blackfin® Processor family of products are
based on an architecture that combines a dual-
MAC, state-of-the-art signal processing engine,
with an orthogonal RISC-like processor
instruction set, and single-instruction, multiple-
data (SIMD) multimedia capabilities into a single
instruction set architecture. By integrating a rich
set of industry leading system peripherals and
memory, Blackfin Processors are the platform of
choice for next generation applications that
require RISC like programmability, multimedia
support and leading edge signal processing in
one integrated Processor.
Typical Blackfin Processor applications such as
video Tele-conferencing systems, digital imaging
products or Personal Digital Assistants (PDAs)
all have a general for a display capability.
This EE-Note describes the hardware and
software environment necessary to provide an
interface between the EPSON S1D13806
Embedded Memory Display Controller and the
ADSP-BF535 High Performance 300 MHz,
Blackfin Processor.
The designs described in this document are
presented only as examples of how such
interfaces might be implemented.
S1D13806 Embedded Memory Display Controller
The S1D13806 is a highly integrated color
LCD/CRT/TV graphics controller with
embedded memory supporting a wide range of
CPUs and display devices. The S1D13806
architecture is designed to meet the low cost, low
power requirements of the embedded markets,
such as Mobile Communications. The S1D13806
supports all LCD panel types, CRT, TV, and
additionally provides a number of differentiating
features.
•
1280K bytes of embedded DRAM
•
Resolutions up to:
•
800x600 at a color depth of 16 bpp.
•
1024x768 at a color depth of 8 bpp.
O v e r v i e w
The ADSP-BF535 System Bus
The External Bus Interface Unit (EBIU) on the
ADSP-BF535 provides a high performance
interface to a wide variety of industry-standard
memory and I/O devices. The asynchronous
memory controller provides a configurable
interface for up to four separate banks of
memory or I/O devices. Each bank occupies a
64M-byte window in the processor’s address
space bus system. The banks can also be
configured for either 16-bit wide or 32-bit wide
buses. Word or byte accesses can be controlled
by the Asynchronous Byte Enable signals
(
/ABE[x]
).
Copyright 2003, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of
customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property
of their respective holders. Information furnished by Analog Devices Applications and Development Tools Engineers is believed to be accurate and reliable, however
no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’ Engineer-to-Engineer Notes.
"Loading the manual" means you need to wait until the file loads and becomes available for online reading. Some manuals are very large, and the time they take to appear depends on your internet speed.
Other Manuals for Epson P-0082
Summary
a This section provides an overview of the operation of the CPU bus in order to establish interface requirements. Asynchronous Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus ( ADD[2:25] , /ABE3 ), the LCD chip select ( /CS ) is driven low by /AM...
a address ( ADDR[2:20] , /ABE3 ) and data bus ( DATA[0:15] ), respectively. CONF[3:0] must be set to select the Generic Host Bus Interface with little endian mode. • M/R (memory/register) selects between memory or register access. It may be connected to an address line, allowing system address ADDR2...
a Interfacing EPSON S1D13806 memory display controller to Blackfin® Processors (EE-184) Page 4 of 13 Figure 2: Typical Implementation of ADSP-BF535 to S1D13806 Interface Register/Memory Mapping The ADSP-BF535 supports four asynchronous memory regions. Each has a unique memory select ( AMS[x] ) assoc...
