Cypress nvSRAM - Manuals

Cypress nvSRAM – Manual in PDF format online.

Manuals:

Manual

Manual Cypress nvSRAM

Summary

Page 2 - PRELIMINARY; Pinouts; Top View

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 2 of 24 Pinouts Figure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44 Pin TSOP II 48-FBGA (not to scale) Top View (x8) 48-FBGA (not to scale) Top View (x16) WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ0 A 4 A 5 NC DQ2 DQ3 NC...

Page 3 - Pin Definitions

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 3 of 24 Figure 3. Pin Diagram - 54 Pin TSOP II (x16) Pin Definitions Pin Name IO Type Description A 0 – A 17 Input Address Inputs Used to Select one of the 262,144 bytes of the nvSRAM for x8 Configuration . A 0 – A 16 Address Inputs...

Page 4 - Device Operation; “Truth Table For SRAM Operations”; SRAM Read; Figure 4; Figure 4. AutoStore Mode; Hardware STORE Operation

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 4 of 24 Device Operation The CY14B102L/CY14B102N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a st...

Page 5 - Software STORE

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 5 of 24 completion of the STORE operation, the CY14B102L/CY14B102N remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used. Hardware RECALL (Power Up) During power up or after any low power condi...

Page 6 - Preventing AutoStore; Noise Considerations

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 6 of 24 Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore ...

Page 7 - Maximum Ratings; DC Electrical Characteristics

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 7 of 24 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................. –65 ° C to +150 ° C Maximum Accumulated Storage T...

Page 8 - AC Test Conditions; Thermal Resistance; OUTPUT

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 8 of 24 AC Test Conditions Input Pulse Levels .................................................... 0V to 3VInput Rise and Fall Times (10% - 90%)........................ <3 nsInput and Output Timing Reference Levels .................

Page 9 - AC Switching Characteristics

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 9 of 24 AC Switching Characteristics Parameters Description 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min Max Min Max SRAM Read Cycle t ACE t ACS Chip Enable Access Time 20 25 45 ns t RC [15] t RC Read Cycle T...

Page 12 - AutoStore/Power Up RECALL

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 12 of 24 AutoStore/Power Up RECALL Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [21] Power Up RECALL Duration 20 20 20 ms t STORE [22] STORE Cycle Duration 8 8 8 ms t DELAY [23] Time Allowed to Com...

Page 13 - Software Controlled STORE/RECALL Cycle; Switching Waveforms

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 13 of 24 Software Controlled STORE/RECALL Cycle In the following table, the software controlled STORE/RECALL cycle parameters are listed. [26, 27] Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t RC STORE/RECA...

Page 14 - Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Soft Sequence Processing Time

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 14 of 24 Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t DHSB HSB To Output Active Time when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Width 15 15 15 ns t SS [28, 29] So...

Page 15 - Truth Table For SRAM Operations; For x8 Configuration

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 15 of 24 Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration CE WE OE Inputs/Outputs [2] Mode Power H X X High Z Deselect/Power down Standby L H L Data Out (DQ 0 –DQ 7 ); Read Active L H ...

Page 16 - Ordering Information

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 16 of 24 Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 20 CY14B102L-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B102L-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14B102L-ZS20XI 51-850...

Page 19 - Part Numbering Nomenclature; Cypress

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 19 of 24 Part Numbering Nomenclature Option:T - Tape & ReelBlank - Std. Speed: 20 - 20ns 45 - 45 ns Data Bus:L - x8 N - x16 Density: 102 - 2 Mb Voltage:B - 3.0V Cypress CY 14 B 102 L - ZS P 20 X C T NVSRAM 14 - Auto Store + Soft...

Page 20 - Package Diagrams

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 20 of 24 Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) MAXMIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016)0.300 (0.012) EJECTOR PIN R G O K E A X S 11.735 ...

Page 23 - Document History Page; Submission

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 23 of 24 Document History Page Document Title: CY14B102L/CY14B102N 2 Mbit (256K x 8/128K x 16) nvSRAM Document Number: 001-45754 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 2470086 GVCH New Data Sheet *A 25...

Page 24 - Worldwide Sales and Design Support

Document #: 001-45754 Rev. *B Revised November 10, 2008 Page 24 of 24 AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. PRELIMINARY CY14B102L, CY14B102N © Cypress Semico...