Page 2 - IFCONFIG; Creating GPIF Waveforms
February 19, 2008 Document No. 001-15342 Rev. ** 2 AN6077 GPIF Master Pin Descriptions The GPIF pin names, descriptions, and their uses are dis-cussed in this section. RDYn Inputs RDY[5:0] are ‘ready’ inputs that can be sampled and allow atransaction to wait (inserting wait states), continue, or rep...
Page 3 - Figure 2; FIFOWR; Figure 3
February 19, 2008 Document No. 001-15342 Rev. ** 3 AN6077 Figure 2 shows the GPIF Designer view of the FIFO Read waveform. FIFOWR When creating the FIFOWR waveform the following timingparameters must be met. tWR pwl - SLWR Pulse Width LOW = 50 ns (minimum) tWR pwh - SLWR Pulse Width HIGH = 50 ns (mi...
Page 4 - Firmware Architecture
February 19, 2008 Document No. 001-15342 Rev. ** 4 AN6077 Figure 4. FIFO Read Waveform in gpif.c Figure 5. FIFO Write Waveform in gpif.c 8051 Firmware Programming (Master) This section describes how to configure the 8051 to supportthe interface on the master side (register settings and others)and di...
Page 5 - the PKTEND of the slave is tied; Psuedocode for Master OUT; if GPIF is IDLE; Psuedocode for Master IN; if the GPIF is IDLE; Expanded Master OUT Code
February 19, 2008 Document No. 001-15342 Rev. ** 5 AN6077 The firmware uses the AUTO mode for both IN and OUTtransfers. This means that the maximum size (512 bytes)packets are committed automatically from the peripheraldomain to the USB domain for OUT transfers. For IN trans-fers, they are committed...
Page 6 - Expanded Master IN Code
February 19, 2008 Document No. 001-15342 Rev. ** 6 AN6077 IOA = 0x80; xFIFOTC_OUT = ( ( EP2FIFOBCH << 8 ) + EP2FIFOBCL ); // setup GPIF transaction count SYNCDELAY; EP2GPIFTCH = EP2FIFOBCH; SYNCDELAY; EP2GPIFTCL = EP2FIFOBCL; // trigger FIFO write transaction(s) SYNCDELAY; GPIFTRIG = GPIFTRIGW...
Page 8 - Code Listing for Master Side
February 19, 2008 Document No. 001-15342 Rev. ** 8 AN6077 Code Listing for Master Side #pragma NOIV // Do not generate interrupt vectors#include "fx2.h"#include "fx2regs.h"#include "fx2sdly.h" // SYNCDELAY macro extern BOOL GotSUD; // Received setup data flagextern BOOL Sleep...
Page 11 - // let transaction terminate naturally
February 19, 2008 Document No. 001-15342 Rev. ** 11 AN6077 // setup GPIF transaction count SYNCDELAY; EP2GPIFTCH = EP2FIFOBCH; SYNCDELAY; EP2GPIFTCL = EP2FIFOBCL; // trigger FIFO write transaction(s), using SFR SYNCDELAY; GPIFTRIG = GPIFTRIGWR | GPIF_EP2; // once master (GPIF) drains OUT packet, it ...
Page 17 - Code Listing for the Slave Side
February 19, 2008 Document No. 001-15342 Rev. ** 17 AN6077 }void ISR_Ep8fflag( void ) interrupt 0{}void ISR_GpifComplete( void ) interrupt 0{}void ISR_GpifWaveform( void ) interrupt 0{ // FIFORd WF detected peripheral prematurely empty (less than max. pkt. size) GPIFABORT = 0xFF; // abort to handle ...