Cypress FS782 - Manuals - manualsarea.com

Page 2 - Pin Description; Table 2; Block Diagram

FS781/82/84 Document #: 38-07029 Rev. *F Page 2 of 12 Output Frequency Selection Loop Filter Selection Chart The following table provides a list of recommended loop filtervalues for the FS781/82/84. The FS78X is divided into fourranges and operated at both 3.3V and 5.5 VDC. The loop filterat the rig...

Page 3 - Input MHz

FS781/82/84 Document #: 38-07029 Rev. *F Page 3 of 12 Table 2. FS781/82/84 Recommended Loop Filter Values C7 (pF) @ +3.3 VDC ±5% (R6 = 3.3K) [1, 2, 3, 4] Input MHz S1 S0 BW = 1.0% [3] BW = 1.5% [3] BW = 2.0% [3] BW = 2.5% [3] BW = 3.0% [3] BW = 3.5% [3] BW = 4.0% [3] 6 0 0 10,000/1000 1550 910 780 7...

Page 5 - SSCG Modulation Profile; Table 4; Theory of Operation; Consider that this 20-MHz clock is applied to the X; input of; Table 4. Modulation Rate Divider Ratios; Figure 1. Frequency Profile in Time Domain

FS781/82/84 Document #: 38-07029 Rev. *F Page 5 of 12 SSCG Modulation Profile The digital control inputs S0 and S1 determine the modulationfrequency of FS781/2/4 products. The input frequency isdivided by a fixed number, depending on the operating rangethat is selected. The modulation frequency of t...

Page 6 - Application Notes and Schematic; Figure 5; Figure 4. Period Comparison Chart

FS781/82/84 Document #: 38-07029 Rev. *F Page 6 of 12 From the above parameters, the output clock at FSOUT will besweeping symmetrically around a center frequency of 20 MHz. The minimum and maximum extremes of this clock will be+200 kHz and –200 kHz. So we have a clock that is sweepingfrom 19.8 MHz ...

Page 8 - Absolute Maximum Ratings

FS781/82/84 Document #: 38-07029 Rev. *F Page 8 of 12 Absolute Maximum Ratings [6] This device contains circuitry to protect the input againstdamage due to high static voltages or electric fields; however,precautions should be taken to avoid application of anyvoltage higher than the absolute maximum...

Page 9 - Ordering Information

FS781/82/84 Document #: 38-07029 Rev. *F Page 9 of 12 CCJ FSOUT, Cycle-to-Cycle Jitter, 48 MHz @ 3.30 VDC (Pin 6) – 320 370 ps CCJ FSOUT, Cycle-to-Cycle Jitter, 48 MHz @ 5.0 VDC (Pin 6) – 310 360 ps CCJ FSOUT, Cycle-to-Cycle Jitter, 72 MHz @ 3.30 VDC (Pin 6) – 270 325 ps CCJ FSOUT, Cycle-to-Cycle Ji...

Page 10 - Cypress Device Driver

FS781/82/84 Document #: 38-07029 Rev. *F Page 10 of 12 Marking Example Package Drawing and Dimensions Cypress FS781BSDate Code, Lot # CypressFS781BTDate Code, Lot # FS781 B S Cypress Device Driver Revision PackageS = SOICT = TSSOP SEATING PLANE PIN 1 ID 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3...

Page 11 - Package Drawing and Dimensions

FS781/82/84 Document #: 38-07029 Rev. *F Page 11 of 12 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress p...

Page 12 - Document History Page; Issue Date

FS781/82/84 Document #: 38-07029 Rev. *F Page 12 of 12 Document History Page Document Title: FS781/82/84 Low EMI Spectrum Spread ClockDocument Number: 38-07029 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106948 06/07/01 IKA Convert from IMI to Cypress *A 111654 02/27/02 IKL Add ...