Cypress CYV15G0404DXB - Manuals

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Manual Cypress CYV15G0404DXB

Summary

Page 2 - CYV15G0404DXB Transceiver Logic Block Diagram

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 2 of 44 The CYV15G0404DXB satisfies the SMPTE-259M andSMPTE-292M compliance according to SMPTE EG34-1999Pathological Test Requirements. As a second generation HOTLink device, the CYV15G0404DXBextends the HOTLink family with enhanced levels of integrati...

Page 3 - Transmit Path Block Diagram; IST LFSR; Transmit PLL; BIST LFS

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 3 of 44 Shif ter TXLBA TXLBC Transmit Path Block Diagram TXRATEA Inpu t Register Phas e-Align Bu ff er Encoder B IST LFSR SPDSELA REFCLKA+ REFCLKA– Transmit PLL Clock Multiplier TXCLKA Bit-Rate Clock Character-Rate Clock A OUTA1+OUTA1– OUTA2+OUTA2– 8 T...

Page 4 - Receive Path Block; Internal Signal

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 4 of 44 INA1+INA1– INA2+INA2– INSELA INB1+INB1– INB2+INB2– INSELB INC1+INC1– INC2+INC2– INSELC IND1+IND1– IND2+IND2– INSELD Clock & Data Recovery PLL Shif ter Clock & Data Recovery PLL Shif ter Clock & Data Recovery PLL Shif ter Clock &...

Page 5 - Device Configuration and Control Block; tion and Control

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 5 of 44 WREN ADDR[3:0] DATA[7:0] Device Configuration and Control Block = Internal Signal RXRATE[A..D] FRAMCHAR[A..D] RFEN[A..D] RXCKSEL[A..D] RFMODE[A..D][1:0] RXBIST[A..D] DECMODE[A..D] DECBYP[A..D] SDASEL[A..D][1:0]RXPLLPD[A..D]TXRATE[A..D]TXCKSEL[A...

Page 8 - Table 3

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 8 of 44 Pin DefinitionsCYV15G0404DXB Quad HOTLink II Transceiver Name I/O Characteristics Signal Description Transmit Path Data and Status Signals TXDA[7:0]TXDB[7:0]TXDC[7:0]TXDD[7:0] LVTTL Input, synchronous, sampled by the associated TXCLKx ↑ or REFC...

Page 9 - Pin Definitions

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 9 of 44 TXCLKOATXCLKOBTXCLKOCTXCLKOD LVTTL Output Transmit Clock Output . TXCLKOx output clock is synthesized by each channel’s transmit PLL and operates synchronous to the internal transmit character clock.TXCLKOx operates at either the same frequency...

Page 13 - Encoder; Table 1. Input Register Bit Assignments

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 13 of 44 Once initialized, TXCLKx is allowed to drift in phase as much as±180 degrees. If the input phase of TXCLKx drifts beyond thehandling capacity of the phase align buffer, TXERRx is assertedto indicate the loss of data, and remains asserted until...

Page 14 - Transmit Modes; Encoder Bypass; Transmit BIST; Transmit PLL Clock Multiplier; Table 4

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 14 of 44 Transmit Modes Encoder Bypass When the Encoder is bypassed, the character captured from theTXDx[7:0] and TXCTx[1:0] input register is passed directly to thetransmit shifter without modification. With the encoder bypassed,the TXCTx[1:0] inputs ...

Page 15 - Serial Output Drivers; Transmit Channels Enabled; Serial Line Receivers; Signal Detect/Link Fault; Analog Amplitude; Table 5. Analog Amplitude Detect Valid Signal Levels

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 15 of 44 The REFCLKx± inputs are differential inputs with each inputinternally biased to 1.4V. If the REFCLKx+ input is connected toa TTL, LVTTL, or LVCMOS clock source, the input signal isrecognized when it passes through the internally biasedreferenc...

Page 16 - remote; Reclocker; Framing Character

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 16 of 44 Transition Density The transition detection logic checks for the absence of transi-tions spanning greater than six transmission characters (60 bits).If no transitions are present in the data received, the detectionlogic for that channel assert...

Page 17 - Receive BIST Operation; Table 6. Framing Character Selector

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 17 of 44 through the FRAMCHARx latches through the configurationinterface. The specific bit combinations of these framing characters arelisted in Table 6 . When the specific bit combination of the selected framing character is detected by the framer, t...

Page 18 - . These same codes are reported on the receive; Receive Elasticity Buffer; Device Reset State; Output Bus; Table 7

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 18 of 44 Code rule violations or running disparity errors that occur as partof the BIST loop do not cause an error indication. RXSTx[2:0]indicates 010b or 100b for one character period per BIST loop toindicate loop completion. This status can be used t...

Page 19 - Table 9

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 19 of 44 When the 10B/8B decoder is bypassed, the framed 10-bit valueis presented to the associated output register, along with a statusoutput signal indicating if the character in the output register isone of the selected framing characters. The bit u...

Page 22 - to synchronize it to the internal clock domain.

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 22 of 44 TXRATEATXRATEBTXRATECTXRATED Transmit PLL Clock Rate Select . The initialization value of the TXRATEx latch = 0. TXRATEx is used to select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the associated ...

Page 23 - Table 10. Device Control Latch Configuration Table

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 23 of 44 Device Configuration Strategy The following is a series of ordered events needed to load theconfiguration latches on a per channel basis: 1. Pulse RESET Low after device power up. This operation resets all four channels. Initialize the JTAG st...

Page 25 - Figure 2. Receive BIST State Machine

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 25 of 44 Figure 2. Receive BIST State Machine Receive BIST Detected LOW Monitor Data Received RXSTx = BIST_START (101) No RX PLL Out of Lock Yes, RXSTx = BIST_DATA_COMPARE (000) / BIST_COMMAND_COMPARE (001) Compare Next Character Auto-Abort Condition M...

Page 26 - Maximum Ratings; Power Up Requirements; Operating Range; CYV15G0404DXB DC Electrical Characteristics

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 26 of 44 Maximum Ratings Exceeding maximum ratings may impair the useful life of device.These user guidelines are not tested. Storage Temperature .................................. –65°C to +150°C Ambient Temperature withPower Applied ....................

Page 28 - CYV15G0404DXB AC Electrical Characteristics; Parameter; CYV15G0404DXB Transmitter LVTTL Switching Characteristics

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 28 of 44 CYV15G0404DXB AC Electrical Characteristics Parameter Description Min. Max Unit CYV15G0404DXB Transmitter LVTTL Switching Characteristics Over the Operating Range f TS TXCLKx Clock Cycle Frequency 19.5 150 MHz t TXCLK TXCLKx Period=1/f TS 6.66...

Page 29 - Over the Operating Range

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 29 of 44 t TREFDS Transmit Data Set-up Time to REFCLKx - Full Rate (TXRATEx = 0, TXCKSELx = 1) 2.4 ns Transmit Data Set-up Time to REFCLKx - Half Rate (TXRATEx = 1, TXCKSELx = 1) 2.3 ns t TREFDH Transmit Data Hold Time from REFCLKx - Full Rate (TXRATEx...

Page 30 - Capacitance; TXCLKx; REFCLKx; Transmit Interface; Write Timing

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 30 of 44 t RISE [20] CML Output Rise Time 20 − 80% (CML Test Load) SPDSELx = HIGH 60 270 ps SPDSELx = MID 100 500 ps SPDSELx =LOW 180 1000 ps t FALL [20] CML Output Fall Time 80 − 20% (CML Test Load) SPDSELx = HIGH 60 270 ps SPDSELx = MID 100 500 ps SP...

Page 31 - CYV15G0404DXB HOTLink II Transmitter Switching Waveforms; REFCLKx selected; TXCLKOx

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 31 of 44 Note 33. When REFCLKx± is configured for half rate operation (TXRATE = 1) and data is captured using REFCLKx instead of a TXCLKx clock. Data is captured using both the rising and falling edges of REFCLKx. CYV15G0404DXB HOTLink II Transmitter S...

Page 32 - Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver; full rate RXCLKx±; REFCLKx Selected; half rate RXCLKx±; REFCLKx Selected; TXERRx; Recovered Clock selected

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 32 of 44 Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver Notes 34. The TXCLKOx output remains at the character rate regardless of the state of TXRATE and does not follow the duty cycle of REFCLKx±.35. The rising edge of TXCLKOx output has...

Page 36 - X3.230 Codes and Notation Conventions; Notation Conventions; . This definition of the 10-bit transmission code is based on; B/10B Transmission Code; The following information describes how the tables are; Transmission Order

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 36 of 44 X3.230 Codes and Notation Conventions Information transmitted over a serial link is encoded eight bits ata time into a 10-bit Transmission Character and then sentserially, bit-by-bit. Information received over a serial link iscollected ten bit...

Page 37 - FE

CYV15G0404DXB Document #: 38-02097 Rev. *B Page 37 of 44 mission of any transmission character, the transmitter selects theproper version of the transmission character based on thecurrent running disparity value, and the transmitter calculates anew value for its running disparity based on the conten...

Page 44 - Document History Page; ISSUE

Document #: 38-02097 Rev. *B Revised December 14, 2007 Page 44 of 44 IBM and ESCON are registered trademarks, and FICON is a trademark, of International Business Machines. HOTLink is a registered trademark and HOTLink II and MultiFrame are trademarks ofCypress Semiconductor. All product and company ...