Cypress CYDC128B08 - Manuals

Page 2 - Figure 1. Top Level Block Diagram

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 2 of 26 Notes: 1. A 0 –A 11 for 4k devices; A 0 –A 12 for 8k devices; A 0 –A 13 for 16k devices. 2. BUSY is an output in master mode and an input in slave mode. IO Control Address Decode Mailboxes INT L INT ...

Page 3 - Pin Configurations

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 3 of 26 Pin Configurations [3, 4, 5, 6, 7] Notes: 3. A12L and A12R are NC pins for CYDC064B16.4. IRR functionality is not supported for the CYDC256B16 device. 5. This pin is A13L for CYDC256B16 device.6. Thi...

Page 5 - Functional Description; Table 1; Pin Definitions

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 5 of 26 Functional Description The CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 are low-power CMOS 4k, 8k,16k x 16, and 8/16k x 8 dual-port static RAMs. Arbitration schemes are included on the ...

Page 6 - Table 3; Output Drive Register; Table 4; Semaphore Operation; Table 5

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 6 of 26 then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (FFF for ...

Page 7 - Architecture

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 7 of 26 When reading a semaphore, all sixteen/eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the...

Page 9 - Electrical Characteristics for V; CC

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 9 of 26 Maximum Ratings [23] (Above which the useful life may be impaired. For user guide- lines, not tested.)Storage Temperature ................................. –65°C to +150°CAmbient Temperature with Pow...

Page 10 - Parameter

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 10 of 26 I IX Input Leakage Current 1.8V 1.8V –1 1 –1 1 µ A 2.5V 2.5V –1 1 –1 1 µ A 3.0V 3.0V –1 1 –1 1 µ A I CC Operating Current (V CC = Max., I OUT = 0 mA) Outputs Disabled Ind. 1.8V 1.8V 25 40 15 25 mA I...

Page 13 - Write Cycle; GND

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 13 of 26 7 AC Test Loads and Waveforms Switching Characteristics for V CC = 1.8V Over the Operating Range [27] Parameter Description CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 CYDC256B16, CYD...

Page 14 - Switching Characteristics for V

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 14 of 26 t HA Address Hold From Write End 0 0 ns t SA [28] Address Set-up to Write Start 0 0 ns t PWE Write Pulse Width 25 40 ns t SD Data Set-up to Write End 20 30 ns t HD Data Hold From Write End 0 0 ns t ...

Page 18 - Switching Waveforms

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 18 of 26 Switching Waveforms Read Cycle No.1 (Either Port Address Access) [36, 37, 38] Read Cycle No.2 (Either Port CE/OE Access) [36, 39, 40] Read Cycle No. 3 (Either Port) [36, 38, 41, 42] Notes: 36. R/W i...

Page 23 - Interrupt Timing Diagrams; Right Side Clears INT

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 23 of 26 Interrupt Timing Diagrams Notes: 55. t HA depends on which enable pin (CE L or R/W L ) is deasserted first. 56. t INS or t INR depends on which enable pin (CE L or R/W L ) is asserted last. Switchin...

Page 24 - Ordering Information

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 24 of 26 Ordering Information 16k x16 1.8V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 40 CYDC256B16-40AXC AZ0AB 100-pin Lead-free TQFP Commercial 55 CYDC25...

Page 25 - Package Diagram

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 25 of 26 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuit...

Page 26 - Document History Page; x 8 ConsuMoBL Dual-Port Static RAM

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08, CYDC064B08 Document #: 001-01638 Rev. *E Page 26 of 26 Document History Page Document Title: CYDC256B16/CYDC128B16/CYDC064B16/CYDC128B08/CYDC064B08 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM Document Number: 001-01638 REV. ECN NO....