Cypress CYD01S36V - Manuals

Cypress CYD01S36V – Manual in PDF format online.

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Manual

Manual Cypress CYD01S36V

Summary

Page 2 - Logic Block Diagram; Dual Ported Array

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 2 of 28 Logic Block Diagram [1] FTSEL L PORTSTD[1:0] L DQ [35:0] L BE [3:0] L CE0 L CE1 L OE L R/W L FTSEL R PORTSTD[1:0] R DQ [35:0] R BE [3:0] R CE0 R CE1 R OE R R/W R A [18:0] L CNT/MSK L ADS L CNTEN L C...

Page 3 - Pin Configurations

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 3 of 28 Pin Configurations Figure 1. Pin Diagram - 256-Ball FBGA (Top View) CYD01S36V/CYD02S36V/36VA/CYD04S36V/CYD09S36V/CYD18S36V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A DQ32L DQ30L DQ28L DQ26L DQ24L DQ22...

Page 4 - Pin Definitions

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 4 of 28 Pin Definitions Left Port Right Port Description A 0L –A 18L A 0R –A 18R Address Inputs . BE 0L –BE 3L BE 0R –BE 3R Byte Enable Inputs . Asserting these signals enables Read and Write operations to ...

Page 5 - Table 2; Address Counter and Mask Register; Table 3

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 5 of 28 Master Reset The FLEx36 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchro- nously to the clocks. An MRST initializes the internal burst counter...

Page 9 - Performing a TAP Reset; Performing a Pause/Restart; Figure 4; Figure 3. Programmable Counter-Mask Register Operation

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 9 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG) [23] The FLEx36 family devices incorporate an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not ...

Page 12 - Electrical Characteristics

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 12 of 28 Maximum Ratings Exceeding maximum ratings [25] may shorten the useful life of the device. User guidelines are not tested.Storage Temperature .................................. –65°C to +150°CAmbien...

Page 13 - Switching Characteristics; Vss; ALL INPUT PULSES; OUTPUT

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 13 of 28 Figure 6. AC Test Load and Waveforms Switching Characteristics Over the Operating Range Parameter Description -167 -133 -100 Unit CYD01S36V CYD02S36V/ CYD02S36VA CYD04S36V CYD09S36V CYD01S36V CYD02...

Page 14 - JTAG Timing

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 14 of 28 t HCM CNT/MSK Hold Time 0.6 0.6 NA NA ns t OE Output Enable to Data Valid 4.4 4.4 5.5 5.5 ns t OLZ [31, 32] OE to Low Z 0 0 0 0 ns t OHZ [31, 32] OE to High Z 0 4.0 0 4.4 0 5.5 0 5.5 ns t CD2 Clock...

Page 15 - JTAG Switching Waveform; Test Clock; Switching Waveforms; Figure 7. Master Reset

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 15 of 28 JTAG Switching Waveform Test Clock Test Mode Select TCK TMS Test Data-InTDI Test Data-OutTDO t TCYC t TMSH t TL t TH t TMSS t TDIS t TDIH t TDOX t TDOV Switching Waveforms Figure 7. Master Reset MR...

Page 16 - Figure 8. Read Cycle

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 16 of 28 Figure 8. Read Cycle [14, 33, 34, 35, 36] Notes 33. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.34. ADS = CNTEN = LOW, and M...

Page 17 - Figure 9. Bank Select Read

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 17 of 28 Figure 9. Bank Select Read [37, 38] Figure 10. Read-to-Write-to-Read (OE = LOW) [36, 39, 40, 41, 42] Notes 37. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank co...

Page 18 - Figure 12. Read with Address Counter Advance

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 18 of 28 Figure 11. Read-to-Write-to-Read (OE Controlled) [36, 39, 41, 42] Figure 12. Read with Address Counter Advance [41] Switching Waveforms (continued) t CYC2 t CL2 t CH2 t HC t SC t HW t SW t HA t SA ...

Page 19 - Figure 13. Write with Address Counter Advance

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 19 of 28 Figure 13. Write with Address Counter Advance [42] Switching Waveforms (continued) t CH2 t CL2 t CYC2 A n A n+1 A n+2 A n+3 A n+4 D n+1 D n+1 D n+2 D n+3 D n+4 A n D n t SAD t HAD t SCN t HCN t SD ...

Page 20 - Figure 14. Counter Reset

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 20 of 28 Figure 14. Counter Reset [43, 44] Notes 43. CE 0 = BE0 – BE3 = LOW; CE 1 = MRST = CNT/MSK = HIGH. 44. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the c...

Page 21 - Figure 15. Readback State of Address Counter or Mask Register

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 21 of 28 Figure 15. Readback State of Address Counter or Mask Register [46, 47, 48, 49] Notes 46. CE 0 = OE = BE0 – BE3 = LOW; CE 1 = R/W = CNTRST = MRST = HIGH. 47. Address in output mode. Host must not be...

Page 23 - Figure 17. Counter Interrupt and Retransmit

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 23 of 28 Figure 17. Counter Interrupt and Retransmit [17, 45, 53, 54, 55, 56] Notes 53. CE 0 = OE = BE0 – BE3 = LOW; CE 1 = R/W = CNTRST = MRST = HIGH. 54. CNTINT is always driven.55. CNTINT goes LOW when t...

Page 24 - CLK; Deselected; Write; Read

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 24 of 28 Figure 18. MailBox Interrupt Timing [57, 58, 59, 60, 61] Switching Waveforms (continued) t CH2 t CL2 t CYC2 CLK L t CH2 t CL2 t CYC2 CLK R 7FFFF t SA t HA A n+3 A n A n+1 A n+2 L_PORT ADDRESS A m A...

Page 25 - Ordering Information

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 25 of 28 Ordering Information 512K × 36 (18-Mbit) 3.3V Synchronous CYD18S36V Dual-Port SRAM Speed( MHz) Ordering Code Package Name Package Type Operating Range 133 CYD18S36V-133BBC BB256B 256-ball Grid Arra...

Page 26 - Package Diagrams

CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev. *G Page 26 of 28 Package Diagrams BOTTOM VIEW TOP VIEW 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K PIN 1 CORNER PIN 1 CORNER 0.20(4X) Ø0.25 M C A B Ø0.05 M C Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K) 0.25 C 0.70±0...

Page 28 - Worldwide Sales and Design Support; Change

Document Number: 38-06076 Rev. *G Revised Decenber 09, 2008 Page 28 of 28 FLEx36 and FLEx36-E are trademarks of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are property of the respective corporations. All productsand company names mentioned in t...