Cypress CY7C68300C - Manuals

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Manual Cypress CY7C68300C

Summary

Page 2 - Applications; Additional Resources; Introduction; Figure 1; Figure 1. Simplified Pinout Selection Flowchart

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 2 of 42 Applications The CY7C68300C/301C and CY7C68320C/321A implementa USB 2.0 bridge for all ATA/ATAPI-6 compliant mass storagedevices, such as the following: • Hard drives • CD-ROM, CD-R/W • DVD-ROM, DVD-RAM, DVD±R/W • MP3...

Page 8 - CY4615C reference design kit CD; CC; CC; CC; CC; RESERVED

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 8 of 42 Pin Descriptions The following table lists the pinouts for the 56-pin SSOP, 56-pinQFN and 100-pin TQFP package options for the AT2LP. Referto the “Pin Diagrams” on page 3 for differences between the 68300C/01C and 683...

Page 9 - “VBUSPWRD” on

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 9 of 42 30 16 23 SDA IO Data signal for I 2 C interface. (See “SCL, SDA” on page 11 ). Apply a 2.2k pull up resistor. 3132 N/A N/A NC No connect. 33 17 24 V CC PWR V CC . Connect to 3.3V power source. 34 18 25 DD0 IO [1] Hi-Z...

Page 10 - “DRVPWRVLD” on; “GPIO Pins” on

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 10 of 42 68 34 41 DA0 O/Z [1] Driven HIGH after 2 ms delay ATA address . 69 35 42 DA1 O/Z [1] Driven HIGH after 2 ms delay ATA address . 70 [3] 36 [3] 43 DRVPWRVLD ( DA2 ) I Input Device presence detect. (See “DRVPWRVLD” on p...

Page 11 - Figure 7

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 11 of 42 Additional Pin Descriptions The following sections provide additional pin information. DPLUS, DMINUS DPLUS and DMINUS are the USB signaling pins; they mustbe tied to the D+ and D– pins of the USB connector. Becauseth...

Page 12 - Table 3. Interrupt Data Bitmap

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 12 of 42 SYSIRQ The SYSIRQ pin provides a way for systems to request servicefrom host software by using the USB Interrupt pipe on endpoint1 (EP1). If the AT2LP has no pending interrupt data to return,USB interrupt pipe data r...

Page 13 - Figure 8. SYSIRQ Latching Algorithm; DRVPWRVLD

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 13 of 42 Figure 8. SYSIRQ Latching Algorithm DRVPWRVLD When this pin is enabled with bit 0 of configuration address0x08 (DRVPWRVLD Enable), the AT2LP informs the host thata removable device, such as a CF card, is present. The...

Page 14 - Reset and Power Considerations,; Pin

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 14 of 42 interface and the attached mass storage device, especially ifUltra DMA Mode is used. VBUS_ATA_ENABLE VBUS_ATA_ENABLE is typically used to indicate to theAT2LP that power is present on VBUS. This pin is polled bythe A...

Page 15 - HID Functions for Button Controls; Table 5; Functional Overview; USB Signaling Speed; ATA Interface; USB; Table 5. HID Data Bitmap

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 15 of 42 HID Functions for Button Controls Cypress’s CY7C68320C/CY7C68321C has the capability ofsupporting Human Interface Device (HID) signaling to thehost. If there is a HID descriptor in the configuration data, the GPIOpin...

Page 18 - Operating Modes; Operational Mode Selection Flow; “Fused Memory Data” on page 19; Figure 10. Operational Mode Selection Flow

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 18 of 42 Operating Modes The different modes of operation and EEPROM informationare presented in the following sections. Operational Mode Selection Flow During the power-up sequence, the AT2LP queries the I 2 C bus for an EEP...

Page 20 - MfgCB

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 20 of 42 MfgCB The mfg_load and mfg_read vendor-specific commands arepassed down through the bulk pipe in the CBWCB portion ofthe CBW. The format of this MfgCB is shown as follows. Byte 0is a vendor-specific command designato...

Page 21 - EEPROM Organization; EEPROM are arranged as follows. In; Figure 11. Snapshot of ‘AT2LP Blaster’ Utility

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 21 of 42 EEPROM Organization The contents of the recommended 256-byte (2048-bit) I 2 C EEPROM are arranged as follows. In Table 11 , the column labeled ‘Required Contents’ contains the values that must beused for proper opera...

Page 35 - Parameter

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 35 of 42 Absolute Maximum Ratings Storage Temperature ............................................................................................................................................–65 ° C to +150 ° C Ambient Tem...

Page 36 - AC Electrical Characteristics; ATA Timing Characteristics; Ordering Information; Part Number; 6 SSOP Lead-free for battery-powered designs

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 36 of 42 AC Electrical Characteristics ATA Timing Characteristics The ATA interface supports ATA PIO modes 0, 3, and 4, UltraDMA modes 2, 3, and 4, and multi-word DMA mode 2, per theATA/ATAPI 6 Specification. The highest enab...

Page 37 - Package Diagrams

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 37 of 42 Package Diagrams Figure 12. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL...

Page 38 - Figure 13. 56-lead Shrunk Small Outline Package 056

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 38 of 42 Figure 13. 56-lead Shrunk Small Outline Package 056 Package Diagrams (continued) 0.095 0.025 0.008 SEATING PLANE 0.420 0.088 .020 0.2920.299 0.395 0.092 BSC 0.110 0.016 0.720 0.0080.0135 0.730 DIMENSIONS IN INCHES MI...

Page 39 - General PCB Layout Recommendations For USB Mass Storage Designs; • EZ-USB FX2LP PCB Design Recommendations

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 39 of 42 General PCB Layout Recommendations For USB Mass Storage Designs The following recommendations must be followed to ensurereliable high-performance operation: • Use at least a four-layer, impedance controlled board to ...

Page 40 - Quad Flat Package No Leads (QFN) Package Design Notes; Surface Mount Assembly of AMKOR’s; Figure 15. Cross-Section of the Area Under the QFN Package; is a plot of solder mask pattern and; Other Design Considerations; Proper Power Up Sequence; PCB Material

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 40 of 42 Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the Printed Circuit Board (PCB)is made by soldering the leads on the bottom surface of thepackage to the PCB. Hence, special att...

Page 41 - Purchase of I

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 41 of 42 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circ...

Page 42 - Document History Paged; Issue Date; See ECN

CY7C68300C/CY7C68301CCY7C68320C/CY7C68321C Document 001-05809 Rev. *A Page 42 of 42 Document History Paged Description Title: CY7C68300C/CY7C68301C/CY7C68320C/CY7C68321C EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI BridgeDocument Number: 001-05809 REV. ECN NO. Issue Date Orig. of Change Description of Change ...