Cypress CY7C68053 - Manuals

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Manual Cypress CY7C68053

Summary

Page 2 - USB Signaling Speed; Special Function Registers; 2 pF capacitor values assumes a trace capacitance

CY7C68053 Document # 001-06120 Rev *F Page 2 of 39 Cypress Semiconductor Corporation’s MoBL-USB  FX2LP18 (CY7C68053) is a low-voltage (1.8 volt) version of the EZ- USB ® FX2LP (CY7C68013A), which is a highly integrated, low-power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, seri...

Page 3 - INT2 Interrupt Request and Enable Registers

CY7C68053 Document # 001-06120 Rev *F Page 3 of 39 3.3 I 2 C™ Bus FX2LP18 supports the I 2 C bus as a master only at 100-/400- KHz. SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to either V CC or V CC_IO , even if no I 2 C device is connected.(Connec...

Page 5 - Reset and Wakeup; Reset Pin; Condition; RESET

CY7C68053 Document # 001-06120 Rev *F Page 5 of 39 3.9 Reset and Wakeup The reset and wakeup pins are described in detail in this section. 3.9.1 Reset Pin The input pin, RESET#, resets the FX2LP18 when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C68053, th...

Page 6 - internal; Register Addresses; Size

CY7C68053 Document # 001-06120 Rev *F Page 6 of 39 3.10 Program/Data RAM This section describes the FX2LP18 RAM. 3.10.1 Size The FX2LP18 has 16 kBytes of internal program/data RAM. No USB control registers appear in this space. Memory maps are shown in Figure 3-3 and Figure 3-4 . 3.10.2 Internal Cod...

Page 7 - Default Full-Speed Alternate Settings; Alternate Setting

CY7C68053 Document # 001-06120 Rev *F Page 7 of 39 vertical columns of Figure 3-5 . When operating in full-speed BULK mode only the first 64 bytes of each buffer are used. For example, in high-speed the maximum packet size is 512 bytes, but in full-speed it is 64 bytes. Even though a buffer is confi...

Page 8 - Default High-Speed Alternate Settings; External FIFO Interface; Architecture; GPIF

CY7C68053 Document # 001-06120 Rev *F Page 8 of 39 3.12.6 Default High-Speed Alternate Settings 3.13 External FIFO Interface The architecture, control signals, and clock rates are presented in this section. 3.13.1 Architecture The FX2LP18 slave FIFO architecture has eight 512-byte blocks in the endp...

Page 9 - ECC Generation; ECC Implementation; USB Uploads and Downloads; C Port Pins

CY7C68053 Document # 001-06120 Rev *F Page 9 of 39 3.14.1 Three Control OUT Signals The 56-pin package brings out three of these signals, CTL0–CTL2. The 8051 programs the GPIF unit to define the CTL waveforms. CTLx waveform edges can be programmed to make transitions as fast as once per clock cycle ...

Page 10 - Pin Assignments; Table 3-6. Strap Boot EEPROM Address Lines to These; Port

CY7C68053 Document # 001-06120 Rev *F Page 10 of 39 3.18.2 I 2 C Interface Boot Load Access At power on reset the I 2 C interface boot loader loads the VID/PID/DID and configuration bytes and up to 16 kBytes of program/data. The available RAM spaces are 16 kBytes from 0x0000–0x3FFF and 512 bytes fro...

Page 12 - Appropriate bulk/bypass capacitance should be provided for this

CY7C68053 Document # 001-06120 Rev *F Page 12 of 39 4.1 CY7C68053 Pin Descriptions Note 9. Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in standby. Note also that no pins should be driven wh...

Page 16 - Register Summary; FX2LP18 register bit definitions are described in the

CY7C68053 Document # 001-06120 Rev *F Page 16 of 39 5.0 Register Summary FX2LP18 register bit definitions are described in the MoBL-USB TRM in greater detail. Table 5-1. FX2LP18 Register Summary Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access GPIF Waveform Memories E400 128 WAVEDATA...

Page 23 - W drive level

CY7C68053 Document # 001-06120 Rev *F Page 23 of 39 6.0 Absolute Maximum Ratings Storage Temperature ...........................................................................................................................................– 65°C to +150°CAmbient Temperature with Power SuppliedIndus...

Page 24 - DC Characteristics; Parameter

CY7C68053 Document # 001-06120 Rev *F Page 24 of 39 8.0 DC Characteristics Table 8-1. DC Characteristics Parameter Description Conditions Min. Typ. Max. Unit AV CC 3.3 V supply (to Osc. and PHY) [15] 3.00 3.3 3.60 V V CC_IO 1.8V to 3.3V supply (to I/O) 1.71 1.8 3.60 V V CC_A 1.8 V supply to Analog C...

Page 25 - AC Electrical Characteristics; USB Transceiver; CTL

CY7C68053 Document # 001-06120 Rev *F Page 25 of 39 9.0 AC Electrical Characteristics 9.1 USB Transceiver USB 2.0-compliant in full- and high-speed modes. 9.2 GPIF Synchronous Signals 8 DATA(output) t XGD IFCLK RDY X DATA(input) valid t SRY t RYH t IFCLK t SGD CTL X t XCTL t DAH N N+1 GPIFADR[8:0] t...

Page 26 - Slave FIFO Synchronous Read

CY7C68053 Document # 001-06120 Rev *F Page 26 of 39 9.3 Slave FIFO Synchronous Read IFCLK SLRD FLAGS SLOE t SRD t RDH t OEon t XFD t XFLG DATA t IFCLK N+1 t OEoff N Figure 9-2. Slave FIFO Synchronous Read Timing Diagram [17] Table 9-3. Slave FIFO Synchronous Read Parameters with Internally Sourced I...

Page 27 - Slave FIFO Asynchronous Read; Figure 9-3. Slave FIFO Asynchronous Read Timing Diagram; Table 9-5. Slave FIFO Asynchronous Read Parameters

CY7C68053 Document # 001-06120 Rev *F Page 27 of 39 9.4 Slave FIFO Asynchronous Read SLRD FLAGS t RDpwl t RDpwh SLOE t XFLG t XFD DATA t OEon t OEoff N+1 N Figure 9-3. Slave FIFO Asynchronous Read Timing Diagram [17] Note 20. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 ...

Page 28 - Slave FIFO Synchronous Write

CY7C68053 Document # 001-06120 Rev *F Page 28 of 39 9.5 Slave FIFO Synchronous Write Z Z t SFD t FDH DATA IFCLK SLWR FLAGS t WRH t XFLG t IFCLK t SWR N Figure 9-4. Slave FIFO Synchronous Write Timing Diagram [17] Table 9-6. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK [18] P...

Page 30 - Slave FIFO Asynchronous Packet End Strobe; Table 9-11. Slave FIFO Asynchronous Packet End Strobe Parameters

CY7C68053 Document # 001-06120 Rev *F Page 30 of 39 There is no specific timing requirement that needs to be met for asserting the PKTEND pin with regards to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFO’s or thereafter. The only consideration is that the set-...

Page 33 - Sequence Diagram; Single and Burst Synchronous Read Example; Figure 9-14. Slave FIFO Synchronous Sequence of Events Diagram

CY7C68053 Document # 001-06120 Rev *F Page 33 of 39 9.13 Sequence Diagram Various sequence diagrams and examples are presented in this section. 9.13.1 Single and Burst Synchronous Read Example Figure 9-13 shows the timing relationship of the SLAVE FIFO signals during a synchronous FIFO read using IF...

Page 34 - Single and Burst Synchronous Write

CY7C68053 Document # 001-06120 Rev *F Page 34 of 39 9.13.2 Single and Burst Synchronous Write Figure 9-15 shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchronizing clock. The diagram illustrates a single write followed by burst write of 3 byt...

Page 35 - Sequence Diagram of a Single and Burst Asynchronous Read

CY7C68053 Document # 001-06120 Rev *F Page 35 of 39 9.13.3 Sequence Diagram of a Single and Burst Asynchronous Read Figure 9-16 illustrates the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read. It shows a single read followed by a burst read. • At t = 0, the FIFO addres...

Page 36 - Sequence Diagram of a Single and Burst Asynchronous Write

CY7C68053 Document # 001-06120 Rev *F Page 36 of 39 9.13.4 Sequence Diagram of a Single and Burst Asynchronous Write Figure 9-18 illustrates the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single write followed by a burst write of 3 bytes and committing t...

Page 37 - The FX2LP18 is available in a 56-pin VFBGA package.; Ordering Code; MoBL-USB FX2LP18 Development Kit

CY7C68053 Document # 001-06120 Rev *F Page 37 of 39 10.0 Ordering Information 11.0 Package Diagram The FX2LP18 is available in a 56-pin VFBGA package. Figure 11-1. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 Table 10-1. Ordering Information Ordering Code Package Type RAM Size # Prog I/Os 80...

Page 38 - PCB Layout Recommendations

CY7C68053 Document # 001-06120 Rev *F Page 38 of 39 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress prod...

Page 39 - Document History Page; Document Title: CY7C68053 MoBL-USB FX2LP18 USB Microcontroller

CY7C68053 Document # 001-06120 Rev *F Page 39 of 39 Document History Page Document Title: CY7C68053 MoBL-USB FX2LP18 USB Microcontroller Document Number: 001-06120 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 430449 03/03/06 OSG New data sheet *A 434754 03/24/06 OSG In Section 3....