Cypress CY7C68033 - Manuals

Page 2 - Default NAND Firmware Features; Mass Storage; Overview

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 2 of 33 Default NAND Firmware Features Because the NX2LP-Flex™ is intended for NANDFlash-based USB mass storage applications, a defaultfirmware image is included in the development kit with thefollowing features: • High (480-Mbps) or full (12-Mb...

Page 3 - Functional Overview; USB Signaling Speed; Special Function Registers; C Bus; DVB Unit; GPS Unit; 2-pF capacitor values assumes a trace capacitance

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 3 of 33 Figure 1. Example DVB Block Diagram Figure 2. Example GPS Block Diagram The “Reference Designs” section of the Cypress web siteprovides additional tools for typical USB 2.0 applications. Eachreference design comes complete with firmware ...

Page 6 - Table 4

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 6 of 33 If Autovectoring is enabled (AV2EN = 1 in the INTSET-UPregister), the NX2LP-Flex substitutes its INT2VEC byte.Therefore, if the high byte (‘page’) of a jump-table address ispreloaded at location 0x544, the automatically-insertedINT2VEC b...

Page 8 - Figure 6. Internal Code Memory; RESET

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 8 of 33 Wakeup Pins The 8051 puts itself and the rest of the chip into a power-downmode by setting PCON.0 = 1. This stops the oscillator andPLL. When WAKEUP is asserted by external logic, the oscil-lator restarts, after the PLL stabilizes, and t...

Page 9 - Endpoint RAM; — Bidirectional endpoint zero, 64-byte buffer; Figure 8. Endpoint Configuration; Table 6. Default Full-Speed Alternate Settings

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 9 of 33 Endpoint RAM Size • 3 × 64 bytes (Endpoints 0 and 1) • 8 × 512 bytes (Endpoints 2, 4, 6, 8) Organization • EP0 — Bidirectional endpoint zero, 64-byte buffer • EP1IN, EP1OUT — 64-byte buffers, bulk or interrupt • EP2,4,6,8 — Eight 512-byt...

Page 10 - Default High-Speed Alternate Settings; External FIFO Interface; Architecture; GPIF; Table 7. Default High-Speed Alternate Settings

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 10 of 33 Default High-Speed Alternate Settings External FIFO Interface Architecture The NX2LP-Flex slave FIFO architecture has eight 512-byteblocks in the endpoint RAM that directly serve as FIFOmemories, and are controlled by FIFO control signa...

Page 11 - ECC Generation; C Port Pins

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 11 of 33 the default NAND firmware image implements an 8-bit databus and up to 8 chip enable pins on the GPIF ports, it is recom-mended that designs based upon the default firmware imageuse an 8-bit data bus as well. Each GPIF vector defines the...

Page 12 - Pin Assignments; Figure 9; Figure 9. Port and Signal Mapping

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 12 of 33 Pin Assignments Figure 9 and Figure 10 identify all signals for the 56-pin NX2LP-Flex package. Three modes of operation are available for the NX2LP-Flex:Port mode, GPIF Master mode, and Slave FIFO mode. Thesemodes define the signals on ...

Page 18 - Register Summary

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 18 of 33 Register Summary NX2LP-Flex register bit definitions are described in the EZ-USB TRM in greater detail. Some registers that are listed here and inthe TRM do not apply to the NX2LP-Flex. They are kept here for consistency reasons only. R...

Page 24 - Absolute Maximum Ratings; Operating Conditions

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 24 of 33 Absolute Maximum Ratings Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Supplied ...... 0°C to +70°C Supply Voltage to Ground Potential ............... –0.5V to +4.0V DC Input Volta...

Page 28 - Sequence Diagram of a Single and Burst Asynchronous Read; ns; ns

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 28 of 33 Slave FIFO Asynchronous Address Figure 16. Slave FIFO Asynchronous Address Timing Diagram [13] Sequence Diagram Sequence Diagram of a Single and Burst Asynchronous Read Figure 17. Slave FIFO Asynchronous Read Sequence and Timing Diagram...

Page 29 - Sequence Diagram of a Single and Burst Asynchronous Write

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 29 of 33 Figure 17 diagrams the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read. It shows a singleread followed by a burst read. • At t = 0 the FIFO address is stable and the SLCS signal is asserted. • At t = 1, SL...

Page 31 - PCB Layout Recommendations; Surface Mount Assembly of AMKOR’s; Figure 21. Cross-section of the Area Underneath the QFN Package.; PCB Material

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 31 of 33 PCB Layout Recommendations [16] The following recommendations should be followed to ensurereliable high-performance operation: • At least a four-layer impedance controlled boards is recom- mended to maintain signal quality. • Specify im...

Page 33 - Document History Page; Issue Date

CY7C68033/CY7C68034 Document #: 001-04247 Rev. *D Page 33 of 33 Document History Page Document Title: CY7C68033/CY7C68034 EZ-USB NX2LP-Flex™ Flexible USB NAND Flash ControllerDocument #: 001-04247 Rev. *D REV. ECN NO. Issue Date Orig. of Change Description of Change ** 388499 See ECN GIR Preliminary...