Cypress CY7C68016A - Manuals

Page 2 - Smart; Logic Block Diagram

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 2 of 62 1.1 Features (CY7C68013A/14A only) ■ CY7C68014A: Ideal for battery powered applications ❐ Suspend current: 100 μ A (typ) ■ CY7C68013A: Ideal for non-battery powered applications ❐ Suspend current: 300 μ A (typ) ■ ...

Page 3 - Functional Overview; USB Signaling Speed; Table 1; C Bus; Figure 1. Crystal Configuration; 2-pF capacitor values assumes a trace capacitance

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 3 of 62 2. Applications ■ Portable video recorder ■ MPEG/TV conversion ■ DSL modems ■ ATA interface ■ Memory card readers ■ Legacy conversion devices ■ Cameras ■ Scanners ■ Home PNA ■ Wireless LAN ■ MP3 players ■ Networki...

Page 4 - INT2 Interrupt Request and Enable Registers

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 4 of 62 3.5 USB Boot Methods During the power up sequence, internal logic checks the I 2 C port for the connection of an EEPROM whose first byte is either 0xC0or 0xC2. If found, it uses the VID/PID/DID values in the EEPRO...

Page 5 - Table 4

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 5 of 62 The FX2LP jump instruction is encoded as follows: If Autovectoring is enabled (AV2EN = 1 in the INTSET-UPregister), the FX2LP substitutes its INT2VEC byte. Therefore, ifthe high byte (“page”) of a jump-table addre...

Page 6 - Reset and Wakeup; Figure 2; Table 4. Individual FIFO/GPIF Interrupt Sources

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 6 of 62 If Autovectoring is enabled (AV4EN = 1 in the INTSET-UPregister), the FX 2LP substitutes its INT4VEC byte. Therefore, ifthe high byte (“page”) of a jump-table address is preloaded atlocation 0x0054, the automatica...

Page 7 - Figure 2. Reset Timing Plots; RESET

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 7 of 62 3.9.2 Wakeup Pins The 8051 puts itself and the rest of the chip into a power downmode by setting PCON.0 = 1. This stops the oscillator and PLL.When WAKEUP is asserted by external logic the oscillatorrestarts after...

Page 8 - C interface boot access

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 8 of 62 Figure 3. Internal Code Memory, EA = 0 Inside FX2LP Outside FX2LP 7.5 KBytesUSB regs and 4K FIFO buffers (RD#,WR#) 0.5 KBytes RAM Data (RD#,WR#)* (OK to populatedata memoryhere—RD#/WR#strobes are notactive) 40 KBy...

Page 10 - Figure 5. Endpoint Configuration

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 10 of 62 3.12 Endpoint RAM 3.12.1 Size ■ 3× 64 bytes (Endpoints 0 and 1) ■ 8 × 512 bytes (Endpoints 2, 4, 6, 8) 3.12.2 Organization ■ EP0 ■ Bidirectional endpoint zero, 64 byte buffer ■ EP1IN, EP1OUT ■ 64 byte buffers, bu...

Page 11 - External FIFO Interface; Table 6. Default Full-Speed Alternate Settings; Table 7. Default High-Speed Alternate Settings

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 11 of 62 3.12.5 Default Full-Speed Alternate Settings 3.12.6 Default High-Speed Alternate Settings 3.13 External FIFO Interface 3.13.1 Architecture The FX2LP slave FIFO architecture has eight 512 byte blocks inthe endpoin...

Page 12 - USB Uploads and Downloads

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 12 of 62 3.13.3 GPIF and FIFO Clock Rates An 8051 register bit selects one of two frequencies for the inter-nally supplied interface clock: 30 MHz and 48 MHz. Alternatively,an externally supplied clock of 5 MHz–48 MHz fee...

Page 13 - C Controller; C Port Pins; Compatible with Previous Generation; Cypress web site

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 13 of 62 3.18 I 2 C Controller FX2LP has one I 2 C port that is driven by two internal controllers, one that automatically operates at boot time to load VID/PID/DIDand configuration information, and another that the 8051 ...

Page 14 - Differences; Figure 6

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 14 of 62 3.20 CY7C68013A/14A and CY7C68015A/16A Differences CY7C68013A is identical to CY7C68014A in form, fit, andfunctionality. CY7C68015A is identical to CY7C68016A in form,fit, and functionality. CY7C68014A and CY7C68...

Page 15 - Port

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 15 of 62 Figure 6. Signal RDY0RDY1 CTL0CTL1CTL2 INT0#/PA0INT1#/PA1PA2WU2/PA3PA4PA5PA6PA7 56 BKPT PORTC7/GPIFADR7PORTC6/GPIFADR6PORTC5/GPIFADR5PORTC4/GPIFADR4PORTC3/GPIFADR3PORTC2/GPIFADR2PORTC1/GPIFADR1PORTC0/GPIFADR0 PE7...

Page 16 - programmable; polarity

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 16 of 62 Figure 7. CY7C68013A/CY7C68014A 128-pin TQFP Pin Assignment CLKOUTVCCGNDRDY0/*SLRDRDY1/*SLWRRDY2RDY3RDY4RDY5AVCCXTALOUTXTALINAGNDNCNCNCAVCCDPLUSDMINUSAGNDA11A12A13A14A15VCCGNDINT4T0T1T2*IFCLKRESERVEDBKPTEASCLSDAO...

Page 17 - * denotes programmable polarity

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 17 of 62 Figure 8. CY7C68013A/CY7C68014A 100-pin TQFP Pin Assignment PD0/FD8 *WAKEUP VCC RESET# CTL5 GND PA7/*FLAGD/SLCS# PA6/*PKTEND PA5/FIFOADR1PA4/FIFOADR0 PA3/*WU2 PA2/*SLOE PA1/INT1#PA0/INT0# VCC GND PC7/GPIFADR7PC6/...

Page 29 - Table 12. FX2LP Register Summary

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 29 of 62 5. Register Summary FX2LP register bit definitions are described in the FX2LP TRM in greater detail. Table 12. FX2LP Register Summary Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access GPIF Waveform...

Page 36 - Thermal Characteristics

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 36 of 62 6. Absolute Maximum Ratings Storage Temperature ..................................................................................................................................................... 65°C to +150°C...

Page 37 - USB Transceiver

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 37 of 62 9. DC Characteristics 9.1 USB Transceiver USB 2.0 compliant in full-speed and high-speed modes. 10. AC Electrical Characteristics 10.1 USB Transceiver USB 2.0 compliant in full-speed and high-speed modes. Table 1...

Page 38 - Program Memory Read

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 38 of 62 10.2 Program Memory Read Figure 12. Program Memory Read Timing Diagram t CL t DH t SOEL t SCSL PSEN# D[7..0] OE# A[15..0] CS# t STBL data in t ACC1 t AV t STBH t AV CLKOUT [17] [18] Table 15. Program Memory Read ...

Page 39 - Data Memory Read

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 39 of 62 10.3 Data Memory Read Figure 13. Data Memory Read Timing Diagram data in t CL A[15..0] t AV t AV RD# t STBL t STBH t DH D[7..0] data in t ACC1 [19] t DSU Stretch = 0 Stretch = 1 t CL A[15..0] t AV RD# t DH D[7..0...

Page 40 - Data Memory Write

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 40 of 62 10.4 Data Memory Write Figure 14. Data Memory Write Timing Diagram When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#or WR# are active. The ad...

Page 41 - PORTC Strobe Feature Timings; and; Figure 15. WR# Strobe Function when PORTC is Accessed by 8051

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 41 of 62 10.5 PORTC Strobe Feature Timings The RD# and WR# are present in the 100-pin version and the128-pin package. In these 100-pin and 128-pin versions, an8051 control bit can be set to pulse the RD# and WR# pins when...

Page 42 - GPIF Synchronous Signals; CTL

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 42 of 62 10.6 GPIF Synchronous Signals Figure 17. GPIF Synchronous Signals Timing Diagram [20] DATA(output) t XGD IFCLK RDY X DATA(input) valid t SRY t RYH t IFCLK t SGD CTL X t XCTL t DAH N N+1 GPIFADR[8:0] t SGA Table 1...

Page 43 - Slave FIFO Synchronous Read

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 43 of 62 10.7 Slave FIFO Synchronous Read Figure 18. Slave FIFO Synchronous Read Timing Diagram [20] IFCLK SLRD FLAGS SLOE t SRD t RDH t OEon t XFD t XFLG DATA t IFCLK N+1 t OEoff N Table 20. Slave FIFO Synchronous Read P...

Page 44 - Slave FIFO Asynchronous Read

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 44 of 62 10.8 Slave FIFO Asynchronous Read Figure 19. Slave FIFO Asynchronous Read Timing Diagram [20] SLRD FLAGS t RDpwl t RDpwh SLOE t XFLG t XFD DATA t OEon t OEoff N+1 N Table 22. Slave FIFO Asynchronous Read Paramete...

Page 45 - Slave FIFO Synchronous Write

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 45 of 62 10.9 Slave FIFO Synchronous Write Figure 20. Slave FIFO Synchronous Write Timing Diagram [20] Z Z t SFD t FDH DATA IFCLK SLWR FLAGS t WRH t XFLG t IFCLK t SWR N Table 23. Slave FIFO Synchronous Write Parameters w...

Page 47 - Slave FIFO Asynchronous Packet End Strobe

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 47 of 62 There is no specific timing requirement that should be met forasserting PKTEND pin to asserting SLWR. PKTEND can beasserted with the last data value clocked into the FIFOs or there-after. The setup time t SPE and...

Page 48 - Slave FIFO Output Enable

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 48 of 62 10.13 Slave FIFO Output Enable Figure 25. Slave FIFO Output Enable Timing Diagram [20] 10.14 Slave FIFO Address to Flags/Data Figure 26. Slave FIFO Address to Flags/Data Timing Diagram [20] Table 29. Slave FIFO O...

Page 50 - Single and Burst Synchronous Read Example; Figure 30. Slave FIFO Synchronous Sequence of Events Diagram

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 50 of 62 10.17 Sequence Diagram 10.17.1 Single and Burst Synchronous Read Example Figure 29. Slave FIFO Synchronous Read Sequence and Timing Diagram [20] Figure 30. Slave FIFO Synchronous Sequence of Events Diagram Figure...

Page 51 - Single and Burst Synchronous Write

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 51 of 62 10.17.2 Single and Burst Synchronous Write Figure 31. Slave FIFO Synchronous Write Sequence and Timing Diagram [20] The Figure 31 shows the timing relationship of the SLAVE FIFO signals during a synchronous write...

Page 52 - and minimum de-active pulse width of; . If SLCS is used then, SLCS must be asserted before; from the activating edge of SLRD. In; In burst read mode, during SLOE is assertion, the data bus

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 52 of 62 10.17.3 Sequence Diagram of a Single and Burst Asynchronous Read Figure 32. Slave FIFO Asynchronous Read Sequence and Timing Diagram [20] Figure 33. Slave FIFO Asynchronous Read Sequence of Events Diagram Figure ...

Page 53 - Sequence Diagram of a Single and Burst Asynchronous Write

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 53 of 62 10.17.4 Sequence Diagram of a Single and Burst Asynchronous Write Figure 34. Slave FIFO Asynchronous Write Sequence and Timing Diagram [20] Figure 34 shows the timing relationship of the SLAVE FIFO write in an as...

Page 54 - Ordering Information; EZ-USB FX2LP Development Kit

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 54 of 62 11. Ordering Information Table 33. Ordering Information Ordering Code Package Type RAM Size # Prog IOs 8051 Address /Data Busses Ideal for battery powered applications CY7C68014A-128AXC 128 TQFP – Lead-Free 16K 4...

Page 55 - The FX2LP is available in five packages:; Package Diagrams

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 55 of 62 12. Package Diagrams The FX2LP is available in five packages: ■ 56-pin SSOP ■ 56-pin QFN ■ 100-pin TQFP ■ 128-pin TQFP ■ 56-ball VFBGA Package Diagrams 51-85062-*C Figure 35. 56-lead Shrunk Small Outline Package ...

Page 56 - SOLDERABLE

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 56 of 62 Package Diagrams (continued) 51-85144-*D Figure 36. 56-Lead QFN 8 x 8 mm LF56A (51-85144) TOP VIEW 0.80[0.031] 7.70[0.303] 7.90[0.311] A C 1.00[0.039] MAX. N BOTTOM VIEW SEATING PLANE N 2 0.18[0.007] 0.50[0.020] ...

Page 59 - PCB Layout Recommendations; To control impedance, maintain trace widths and trace spacing.

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 59 of 62 13. PCB Layout Recommendations Follow these recommendations to ensure reliable high perfor-mance operation: [24] ■ Four layer impedance controlled boards are required to maintain signal quality. ■ Specify impedan...

Page 60 - Figure 40. Cross-section of the Area Underneath the QFN Package; PCB Material

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 60 of 62 14. Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the Printed Circuit Board (PCB)is made by soldering the leads on the bottom surface of thepackage to the PCB. Hence, spe...

Page 61 - Document History Page; Issue; Figure 1

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 61 of 62 Document History Page Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral ControllerDocument Number: 38-08032 REV. ECN NO. Issue Date Orig. ...

Page 62 - MON; Min value in

Document #: 38-08032 Rev. *L Revised February 8, 2008 Page 62 of 62 Purchase of I 2 C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I 2 C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the ...