Cypress CY7C67300 - Manuals

CY7C67300 Document #: 38-08015 Rev. *J Page 5 of 99 External Memory Interface EZ-Host provides a robust interface to a wide variety of externalmemory arrays. All available external memory array locationscan contain either code or data. The CY16 RISC processordirectly addresses a flat memory space fr...

CY7C67300 Document #: 38-08015 Rev. *J Page 7 of 99 Figure 4 illustrates the interface for connecting an 8-bit ROM or 8-bit RAM to the EZ-Host external memory interface. In 8-bitmode, up to 512K bytes of external ROM or RAM are supported. General Purpose IO Interface (GPIO) EZ-Host has up to 32 GPIO...

CY7C67300 Document #: 38-08015 Rev. *J Page 8 of 99 SPI Pins The SPI port has a few different pin location options as shown in Table 9 . The port location is selectable via the GPIO control register [0xC006]. High-Speed Serial Interface EZ-Host provides an HSS interface. The HSS interface is aprogra...

CY7C67300 Document #: 38-08015 Rev. *J Page 9 of 99 Host Port Interface EZ-Host has an HPI interface. The HPI interface provides DMAaccess to the EZ-Host internal memory by an external host, plusa bidirectional mailbox register for supporting high level commu-nication protocols. This port is designe...

CY7C67300 Document #: 38-08015 Rev. *J Page 10 of 99 IDE Features ■ Programmable IO mode 0–4 ■ Block mode transfers ■ Direct memory access to/from internal memory through the IDE data register IDE Pins Charge Pump Interface VBUS for the USB OTG port can be produced by EZ-Host usingits built in charg...

CY7C67300 Document #: 38-08015 Rev. *J Page 11 of 99 Booster Interface EZ-Host has an on chip power booster circuit for use with powersupplies that range between 2.7V and 3.6V. The booster circuitboosts the power to 3.3V nominal to supply power for the entirechip. The booster circuit requires an ext...

CY7C67300 Document #: 38-08015 Rev. *J Page 12 of 99 Boot Configuration Interface EZ-Host can boot into any one of four modes. The mode it bootsinto is determined by the TTL voltage level of GPIO[31:30] at thetime nRESET is deasserted. Table 19 shows the different boot pin combinations possible. Aft...

CY7C67300 Document #: 38-08015 Rev. *J Page 13 of 99 Minimum Hardware Requirements for Standalone Mode – Peripheral Only Power Savings and Reset Description This sections describes the different modes for resetting the chipand ways to save power. Power Saving Mode Description EZ-Host has one main po...

CY7C67300 Document #: 38-08015 Rev. *J Page 14 of 99 External (Remote) Wakeup Source There are several possible events available to wake EZ-Hostfrom Sleep mode as shown in Table 20 . These may also be used as remote wakeup options for USB applications. See the Power Control Register [0xC00A] [R/W] o...

CY7C67300 Document #: 38-08015 Rev. *J Page 15 of 99 Figure 10. Memory Map HW INT's SW INT's 0x0000 - 0x00FF Primary Registers Swap Registers USB Registers HPI Int / Mailbox Slave Setup Packet BIOS USER SPACE ~15K Internal Memory External Memory Control Registers USER SPACE 16K USER SPACE ~8K 01 Ext...

CY7C67300 Document #: 38-08015 Rev. *J Page 16 of 99 Registers Some registers have different functions for a read vs. a writeaccess or USB host vs. USB device mode. Therefore, registersof this type have multiple definitions for the same address. The default register values listed in this data sheet ...

CY7C67300 Document #: 38-08015 Rev. *J Page 17 of 99 Bank Register [0xC002] [R/W] Register Description The Bank register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registersR0–R15. A register address is automatically generated by: 1. Shifting the ...

CY7C67300 Document #: 38-08015 Rev. *J Page 18 of 99 CPU Speed Register [0xC008] [R/W] Register Description The CPU Speed register allows the processor to operate at a user selected speed. This register only affects the CPU, all otherperipheral timing is still based on the 48 MHz system clock (unles...

CY7C67300 Document #: 38-08015 Rev. *J Page 21 of 99 HSS Interrupt Enable (Bit 7) The HSS Interrupt Enable bit enables or disables the followingHigh-speed Serial Interface hardware interrupts: HSS BlockDone and HSS RX Full. 1: Enable HSS interrupt 0: Disable HSS interrupt In Mailbox Interrupt Enable...

CY7C67300 Document #: 38-08015 Rev. *J Page 23 of 99 Memory Diagnostic Register [0xC03E] [W] Register Description The Memory Diagnostic register provides control of diagnosticmodes. Memory Arbitration Select (Bits[10:8]) The Memory Arbitration Select field is defined in Table 34 . Monitor Enable (Bi...

CY7C67300 Document #: 38-08015 Rev. *J Page 25 of 99 External Memory Control Register [0xC03A] [R/W] Register Description The External Memory Control register provides control of WaitStates for the external SRAM or ROM. All wait states are basedoff of 48 MHz. XRAM Merge Enable (Bit 13) The XRAM Merg...

CY7C67300 Document #: 38-08015 Rev. *J Page 27 of 99 Timer n Register [R/W] ■ Timer 0 Register 0xC010 ■ Timer 1 Register 0xC012 Register Description The Timer n Register sets the Timer n count. Both Timer 0 andTimer 1 decrement by one every 1 µs clock tick. Each canprovide an interrupt to the CPU wh...

CY7C67300 Document #: 38-08015 Rev. *J Page 29 of 99 Port A SOF/EOP Enable (Bit 0) The Port A SOF/EOP Enable bit is only applicable in host mode.In device mode this bit must be written as ‘0’. In host mode thisbit enables or disables SOFs or EOPs for Port A. Either SOFs orEOPs are generated dependin...

CY7C67300 Document #: 38-08015 Rev. *J Page 32 of 99 Sequence Status (Bit 3) The Sequence Status bit indicates the state of the last receiveddata toggle from the device. Firmware is responsible formonitoring and handling the sequence status. The Sequence bitis only valid if the ACK bit is set to ‘1’...

CY7C67300 Document #: 38-08015 Rev. *J Page 38 of 99 USB Device Only Registers There are eleven sets of USB Device Only registers. All sets consist of at least two registers, one for Device Port 1 and one for DevicePort 2. In addition, each Device port has eight possible endpoints. This gives each e...

CY7C67300 Document #: 38-08015 Rev. *J Page 39 of 99 Sequence Select (Bit 6) The Sequence Select bit determines whether a DATA0 or aDATA1 is sent for the next data toggle. This bit has no effect onreceiving data packets; sequence checking must be handled infirmware. 1: Send a DATA1 0: Send a DATA0 S...

CY7C67300 Document #: 38-08015 Rev. *J Page 48 of 99 Device n SOF/EOP Count Register [W] ■ Device 1 SOF/EOP Count Register 0xC094 ■ Device 2 SOF/EOP Count Register 0xC0B4 Register Description The Device n SOF/EOP Count register is written with the timeexpected between receiving a SOF/EOP. If the SOF...

CY7C67300 Document #: 38-08015 Rev. *J Page 49 of 99 Receive Disable (Bit 12) The Receive Disable bit enables or powers down (disables) theOTG receiver section. 1: OTG receiver powered down and disabled 0: OTG receiver enabled Charge Pump Enable (Bit 11) The Charge Pump Enable bit enables or disable...

CY7C67300 Document #: 38-08015 Rev. *J Page 52 of 99 GPIO n Direction Register [R/W] ■ GPIO 0 Direction Register 0xC022 ■ GPIO 1 Direction Register 0xC028 Register Description The GPIO n Direction register controls the direction of the GPIOdata pins (input/output). The GPIO 0 Direction register cont...

CY7C67300 Document #: 38-08015 Rev. *J Page 55 of 99 IDE PIO Port Registers [0xC050 - 0xC06F] [R/W] All IDE PIO Port registers [0xC050 - 0xC06F] in Table 88 are defined in detail in the Information Technology-AT Attachment -4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev...

CY7C67300 Document #: 38-08015 Rev. *J Page 61 of 99 HPI Registers There are five registers dedicated to HPI operation. In addition,there is an HPI status port which can be addressed over HPI.Each of these registers is covered in this section and are summa-rized in Table 98 . HPI Breakpoint Register...

CY7C67300 Document #: 38-08015 Rev. *J Page 65 of 99 Done1 Flag (Bit 2) In host mode the Done 1 Flag bit is a read only bit that indicatesif a host packet done interrupt occurs on Host 1. In device modethis read only bit indicates if an any of the endpoint interruptsoccur on Device 1. Firmware needs...

CY7C67300 Document #: 38-08015 Rev. *J Page 68 of 99 Receive Bit Length (Bits [2:0]) The Receive Bit Length field controls whether a full byte or partialbyte is received. If Receive Bit Length is ‘000’ then a full byte isreceived. If Receive Bit Length is ‘001’ to ‘111’, then the valueindicates the ...

CY7C67300 Document #: 38-08015 Rev. *J Page 70 of 99 CRC Enable (Bit 13) The CRC Enable bit enables or disables the CRC operation. 1: Enables CRC operation 0: Disables CRC operation CRC Clear (Bit 12) The CRC Clear bit clears the CRC with a load of all ones. Thisbit is self clearing and always reads...

CY7C67300 Document #: 38-08015 Rev. *J Page 73 of 99 Register Description The SPI Receive Count register designates the block byte lengthfor the SPI receive DMA transfer. Count (Bits [10:0]) The Count field sets the count for the SPI receive DMA transfer. Reserved Write all reserved bits with ’0’. U...

CY7C67300 Document #: 38-08015 Rev. *J Page 75 of 99 PWM Registers There are eleven registers dedicated to PWM operation. Each of these registers are covered in this section and summarized in Table 124 . PWM Control Register [0xC0E6] [R/W] Register Description The PWM Control register provides high ...

CY7C67300 Document #: 38-08015 Rev. *J Page 76 of 99 Mode Select (Bit 8) The Mode Select bit selects between continuous PWM cyclingand one shot mode. The default is continuous repeat. 1: Enable One Shot mode. The mode runs the number of counter cycles set in the PWM Cycle Count register and then sto...

CY7C67300 Document #: 38-08015 Rev. *J Page 78 of 99 PWM Cycle Count Register [0xC0FA] [R/W] Register Description The PWM Cycle Count register designates the number of cyclesto run when in one shot mode. One shot mode is enabled bysetting the Mode Select bit of the PWM Control register to ‘1’. Count...

CY7C67300 Document #: 38-08015 Rev. *J Page 79 of 99 Pin Diagram Pin Descriptions 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 G P IO24/INT/IORDY /IR Q 0 GN D A10 XTAL O U T XTAL IN A11 A12 A13 A14 nXMEMS EL nXROMS EL n X R A M SEL VCC A15/C L KSE L GP IO31 /SC L GP IO ...

CY7C67300 Document #: 38-08015 Rev. *J Page 84 of 99 USB Transceiver USB 2.0 certified in full- and low-speed modes. I SLEEP Sleep Current USB Peripheral: includes 1.5K internal pull up 210 500 μ A Without 1.5K internal pull up 5 30 μ A I SLEEPB Sleep Current with Booster Enabled USB Peripheral: inc...

CY7C67300 Document #: 38-08015 Rev. *J Page 85 of 99 AC Timing Characteristics Reset Timing Clock Timing Notes 11. Clock is 12 MHz nominal.12. v XINH is required to be 3.0 V to obtain an internal 50/50 duty cycle clock. Table 135. Reset Timing Parameters Parameter Description Min Typical Max Unit t ...

CY7C67300 Document #: 38-08015 Rev. *J Page 86 of 99 SRAM Read Cycle [15] Notes 13. 0 wait state cycle.14. t AC External SRAM access time = 12 ns for zero and one wait states. The External SRAM access time = 12 ns + (n – 1)*T for wait states = n, n > 1, T = 48 MHz clock period. 15. Read timing is...

CY7C67300 Document #: 38-08015 Rev. *J Page 87 of 99 SRAM Write Cycle [17] Notes 16. t WPW The write pulse width = 18.8 ns min. for zero and one wait states. The write pulse = 18.8 ns + (n – 1)*T for wait states = n, n > 1, T = 48 MHz clock period. 17. Write timing is applicable for nXMEMSEL, nXR...

CY7C67300 Document #: 38-08015 Rev. *J Page 88 of 99 I2C EEPROM Timing-Serial IO Table 139. I2C EEPROM Timing Parameters Parameter Description Min Typical Max Unit f SCL Clock Frequency 400 kHz t LOW Clock Pulse Width Low 1300 ns t HIGH Clock Pulse Width High 600 ns t AA Clock Low to Data Out Valid ...

CY7C67300 Document #: 38-08015 Rev. *J Page 89 of 99 HPI (Host Port Interface) Write Cycle Timing Notes 18. T = system clock period = 1/48 MHz. Table 140. HPI Write Cycle Timing Parameters Parameter Description Min Typical Max Unit t ASU Address Setup –1 ns t AH Address Hold –1 ns t CSSU Chip Select...

CY7C67300 Document #: 38-08015 Rev. *J Page 90 of 99 HPI (Host Port Interface) Read Cycle Timing Table 141. HPI Read Cycle Timing Parameters Parameter Description Min Typical Max Unit t ASU Address Setup –1 ns t AH Address Hold –1 ns t CSSU Chip Select Setup –1 ns t CSH Chip Select Hold –1 ns t ACC ...

CY7C67300 Document #: 38-08015 Rev. *J Page 91 of 99 IDE Timing The IDE interface supports PIO mode 0-4 as specified in the Information Technology-AT Attachment–4 with Packet Interface Extension(ATA/ATAPI-4) Specification, T13/1153D Rev 18. HSS BYTE Mode Transmit qt_clk, CPU_A, CPUHSS_cs, CPU_wr are...

CY7C67300 Document #: 38-08015 Rev. *J Page 92 of 99 Hardware CTS/RTS Handshake t CTSsetup : HSS_CTS setup time before HSS_RTS = 1.5T min. t CTShold : HSS_CTS hold time after START bit = 0 ns min. T = 1/48 MHz. When RTS/CTS hardware handshake is enabled, transmission can be help off by deasserting H...

CY7C67300 Document #: 38-08015 Rev. *J Page 97 of 99 Ordering Information Package Diagrams Figure 12. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100SA Table 143. Ordering Information Ordering Code Package Type AEC Pb-Free Temperature Range CY7C67300-100AXI 100 TQFP X –40 to 85°C CY7C67300-100AXA 10...

CY7C67300 Document #: 38-08015 Rev. *J Page 98 of 99 Document History Page Document Title: CY7C67300 EZ-Host™ Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade SupportDocument Number: 38-08015 REV. ECN NO. Orig. of Change Submis- sion Date Description of Change ** 11...