Cypress CY7C65113C - Manuals

CY7C65113C Document #: 38-08002 Rev. *D Page 5 of 49 1.0 Features • Full Speed USB hub with an integrated microcontroller • 8-bit USB optimized microcontroller — Harvard architecture— 6-MHz external clock source— 12-MHz internal CPU clock— 48-MHz internal hub clock • Internal memory — 256 bytes of R...

CY7C65113C Document #: 38-08002 Rev. *D Page 6 of 49 2.0 Functional Overview The CY7C65113C device is a one-time programmable 8-bit microcontroller with a built-in 12-Mbps USB hub that supports up to four downstream ports. The microcontroller instruction set has been optimized specifically for USB o...

CY7C65113C Document #: 38-08002 Rev. *D Page 7 of 49 Logic Block Diagram Interrupt Controller PROM 12-bit Timer Reset Watchdog Timer Repeater Power-on SCLK I 2 C comp. USB Transceiver USB Transceiver USB Transceiver GPIO PORT 1 GPIO PORT 0 P0[0] P0[7] P1[0] P1[2] SDATA D+[3]D–[3] D+[2]D–[2] 8- bit B...

CY7C65113C Document #: 38-08002 Rev. *D Page 8 of 49 4.0 Product Summary Tables 4.1 Pin Assignments 3.0 Pin Configurations Table 4-1. Pin Assignments Name I/O 28-pin Description D+[0], D–[0] I/O 5, 6 Upstream port, USB differential data. D+[1], D–[1] I/O 7, 8 Downstream Port 1, USB differential data...

CY7C65113C Document #: 38-08002 Rev. *D Page 10 of 49 4.3 Instruction Set Summary Refer to the CYASM Assembler User’s Guide for more details. Note that conditional jump instructions (i.e., JC, JNC, JZ, JNZ) take five cycles if jump is taken, four cycles if no jump. Hub Port Control (Ports [4:1]) 0x4...

CY7C65113C Document #: 38-08002 Rev. *D Page 11 of 49 5.0 Programming Model 5.1 14-bit Program Counter The 14-bit Program Counter (PC) allows access to up to 8 KB of PROM available with the CY7C65113C architecture. The top 32 bytes of the ROM in the 8K part are reserved for testing purposes. The pro...

CY7C65113C Document #: 38-08002 Rev. *D Page 12 of 49 5.1.1 Program Memory Organization Note that the upper 32 bytes of the 8K PROM are reserved. Therefore, user’s program must not overwrite this space. after reset Address 14-bit PC 0x0000 Program execution begins here after a reset 0x0002 USB Bus R...

CY7C65113C Document #: 38-08002 Rev. *D Page 13 of 49 5.2 8-bit Accumulator (A) The accumulator is the general-purpose register for the microcontroller. 5.3 8-bit Temporary Register (X) The “X” register is available to the firmware for temporary storage of intermediate results. The microcontroller c...

CY7C65113C Document #: 38-08002 Rev. *D Page 14 of 49 5.5 8-bit Data Stack Pointer (DSP) The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP, then writes data to the memory location addressed by the ...

CY7C65113C Document #: 38-08002 Rev. *D Page 15 of 49 6.0 Clocking The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to these pins. When using an external crystal, keep PCB traces between the chip leads and crystal as short as ...

CY7C65113C Document #: 38-08002 Rev. *D Page 16 of 49 7.2 Watchdog Reset The WDR occurs when the internal Watchdog Timer rolls over. Writing any value to the write-only Watchdog Reset Clear Register ( Figure 7-1 ) clears the timer. The timer rolls over and WDR occurs if it is not cleared within t WA...

CY7C65113C Document #: 38-08002 Rev. *D Page 18 of 49 9.1 GPIO Configuration Port Every GPIO port can be programmed as inputs with internal pull-ups, outputs LOW or HIGH, or Hi-Z (floating, the pin is not driven internally). In addition, the interrupt polarity for each port can be programmed. The Po...

CY7C65113C Document #: 38-08002 Rev. *D Page 19 of 49 Q1, Q2, and Q3 discussed below are the transistors referenced in Figure 9-1 . The available GPIO drive strength are: • Output LOW Mode : The pin’s Data Register is set to ‘0.’ Writing ‘0’ to the pin’s Data Register puts the pin in output LOW mode...

CY7C65113C Document #: 38-08002 Rev. *D Page 20 of 49 Bit [7:0]: Timer lower eight bits. Bit [3:0]: Timer higher nibbleBit [7:4]: Reserved. 11.0 I 2 C Configuration Register Internal hardware supports communication with external devices through an I 2 C-compatible interface. I 2 C-compatible functio...

CY7C65113C Document #: 38-08002 Rev. *D Page 21 of 49 12.0 I2C-compatible Controller The I2C-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and multi-master modes of operation. The I2C-compatible block functions by handling the low-level...

CY7C65113C Document #: 38-08002 Rev. *D Page 23 of 49 13.0 Processor Status and Control Register Bit 0: Run This bit is manipulated by the HALT instruction. When Halt is executed, all the bits of the Processor Status and Control Register are cleared to 0. Since the run bit is cleared, the processor ...

CY7C65113C Document #: 38-08002 Rev. *D Page 24 of 49 14.0 Interrupts Interrupts are generated by GPIO pins, internal timers, I 2 C-compatible operation, internal USB hub and USB traffic conditions. All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt E...

CY7C65113C Document #: 38-08002 Rev. *D Page 25 of 49 During a reset, the contents of the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared, effectively disabling all interrupts,The interrupt controller contains a separate flip-flop for each interrupt. See Figu...

CY7C65113C Document #: 38-08002 Rev. *D Page 26 of 49 Although Reset is not an interrupt, the first instruction executed after a reset is at PROM address 0x0000h—which corresponds to the first entry in the Interrupt Vector Table. Because the JMP instruction is two bytes long, the interrupt vectors o...

CY7C65113C Document #: 38-08002 Rev. *D Page 27 of 49 14.5 USB Endpoint Interrupts There are five USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to a USB endpoint FIFO or after the USB controller sends a packet to the USB host. The interrup...

CY7C65113C Document #: 38-08002 Rev. *D Page 28 of 49 3. In slave transmit mode, after the slave transmits a byte of data: The ACK bit indicates if the master that requested the byte acknowledged the byte. If more bytes are to be sent, firmware writes the next byte into the Data Register and then se...

CY7C65113C Document #: 38-08002 Rev. *D Page 29 of 49 6. The host sends a request for the Device descriptor using the new USB address.7. Firmware decodes the request and retrieves the Device descriptor from program memory tables.8. The host performs a control read sequence and Firmware responds by s...

CY7C65113C Document #: 38-08002 Rev. *D Page 30 of 49 Bit [0..3] : Port x Speed (where x = 1..4). Set to 1 if the device plugged in to Port x is Low Speed; Set to 0 if the device plugged in to Port x is Full Speed. Bit [4..7] : Reserved. Set to 0. The Hub Ports Speed register is cleared to zero by r...

CY7C65113C Document #: 38-08002 Rev. *D Page 32 of 49 . Bit [0..3] : Port x Diff Data (where x = 1..4). Set to 1 if D+ > D- (forced differential 1, if signal is differential, i.e. not a SE0 or SE1). Set to 0 if D- > D+ (forced differential 0, if signal is differential, i.e. not a SE0 or SE1). ...

CY7C65113C Document #: 38-08002 Rev. *D Page 33 of 49 Bit [0..3] : Resume x (where x = 1..4). When set to 1 Port x requesting to be resumed (set by hardware); default state is 0. Bit [4..7] : Reserved. Set to 0. Resume from a selectively suspended port, with the hub not in suspend, typically involve...

CY7C65113C Document #: 38-08002 Rev. *D Page 34 of 49 Bit 3: Bus Activity. This is a “sticky” bit that indicates if any non-idle USB event has occurred on the upstream USB port. Firmware should check and clear this bit periodically to detect any loss of bus activity. Writing a ‘0’ to the Bus Activit...

CY7C65113C Document #: 38-08002 Rev. *D Page 35 of 49 When the SIE writes data to a FIFO, the internal data bus is driven by the SIE; not the CPU. This causes a short delay in the CPU operation. The delay is three clock cycles per byte. For example, an 8-byte data write by the SIE to the FIFO genera...

CY7C65113C Document #: 38-08002 Rev. *D Page 36 of 49 Bits[6:0] of the endpoint 0 mode register are locked from CPU write operations whenever the SIE has updated one of these bits, which the SIE does only at the end of the token phase of a transaction (SETUP... Data... ACK, OUT... Data... ACK, or IN...

CY7C65113C Document #: 38-08002 Rev. *D Page 37 of 49 Bit 6: Data Valid. This bit is set on receiving a proper CRC when the endpoint FIFO buffer is loaded with data during transactions. This bit is used OUT and SETUP tokens only. If the CRC is not correct, the endpoint interrupt occurs, but Data Val...

CY7C65113C Document #: 38-08002 Rev. *D Page 39 of 49 18.0 USB Mode Tables Mode This lists the mnemonic given to the different modes that can be set in the Endpoint Mode Register by writing to the lower nibble (bits 0..3). The bit settings for different modes are covered in the column marked “Mode B...

CY7C65113C Document #: 38-08002 Rev. *D Page 40 of 49 Comments Some Mode Bits are automatically changed by the SIE in response to certain USB transactions. For example, if the Mode Bits [3:0] are set to '1111' which is ACK IN-Status OUT mode as shown in Table 18-1 , the SIE will change the endpoint ...

CY7C65113C Document #: 38-08002 Rev. *D Page 41 of 49 . Table 18-3. Details of Modes for Differing Traffic Conditions (see Table 18-2 for the decode legend) SETUP (if accepting SETUPs) Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits Mode Bits token count buffer ...

CY7C65113C Document #: 38-08002 Rev. *D Page 43 of 49 19.0 Register Summary Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Write/B oth/–[7] Default/ Reset GPIO CONFIGURA TIO N PORTS 0 AND 1 0x00 Port 0 Data P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 BBBBBBBB 11111111 0x01 Po...

CY7C65113C Document #: 38-08002 Rev. *D Page 45 of 49 20.0 Sample Schematic 21.0 Absolute Maximum Ratings Storage Temperature .......................................................................................................................................... –65°C to +150°CAmbient Temperature ...

CY7C65113C Document #: 38-08002 Rev. *D Page 46 of 49 22.0 Electrical Characteristics f OSC = 6 MHz; Operating Temperature = 0 to 70°C, V CC = 4.0V to 5.25V Parameter Description Conditions Min. Max. Unit General V REF Reference Voltage 3.3V ±5% 3.15 3.45 V V pp Programming Voltage (disabled) –0.4 0...

CY7C65113C Document #: 38-08002 Rev. *D Page 47 of 49 23.0 Switching Characteristics (f OSC = 6.0 MHz) Parameter Description Min. Max. Unit Clock Source f OSC Clock Rate 6 ±0.25% MHz t cyc Clock Period 166.25 167.08 ns t CH Clock HIGH time 0.45 t CYC ns t CL Clock LOW time 0.45 t CYC ns USB Full-spe...

CY7C65113C Document #: 38-08002 Rev. *D Page 48 of 49 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress pr...

CY7C65113C Document #: 38-08002 Rev. *D Page 49 of 49 Document History Page Document Title: CY7C65113C USB Hub with Microcontroller Document Number: 38-08002 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109965 02/22/02 SZV Change from Spec number: 38-00590 to 38-08002 *A 120372 1...