Cypress CY7C63413C - Manuals

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Manual

Manual Cypress CY7C63413C

Summary

Page 3 - Logic Block Diagram; Pin Configuration; See Note 1

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 3 of 32 . Note: 1. CY7C63613C is not bonded out for all GPIO pins shown in Logic Block Diagram. Refer to pin configuration diagram for bonded out pins. See note on page 12 for firmware code needed for unused GPIO pins. Logic Block Diag...

Page 4 - Name

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 4 of 32 Programming Model 14-bit Program Counter (PC) The 14-bit Program Counter (PC) allows access for up to 8kilobytes of EPROM using the CY7C63413C/513C/613Carchitecture. The program counter is cleared during reset,such that the fir...

Page 5 - Address Modes; Data

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 5 of 32 During an interrupt acknowledge, interrupts are disabled andthe 14-bit program counter, carry flag, and zero flag are writtenas two bytes of data memory. The first byte is stored in thememory addressed by the program stack poin...

Page 6 - Instruction Set Summary; reserved

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 6 of 32 Instruction Set Summary MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles HALT 00 7 NOP 20 4 ADD A,expr data 01 4 INC A acc 21 4 ADD A,[expr] direct 02 6 INC X x 22 4 ADD A,[X+expr] index 03 7 INC [expr] direct 23 7...

Page 7 - Memory Organization; Program Memory Organization

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 7 of 32 Memory Organization Program Memory Organization after reset Address 14-bit PC 0x0000 Program execution begins here after a reset 0x0002 USB Bus Reset interrupt vector 0x0004 128- µ s timer interrupt vector 0x0006 1.024-ms timer...

Page 10 - WDR goes high

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 10 of 32 Clocking The XTAL IN and XTAL OUT are the clock pins to the microcon- troller. The user can connect a low-cost ceramic resonator oran external oscillator can be connected to these pins toprovide a reference frequency for the i...

Page 11 - General Purpose I/O Ports; The internal pull-up resistors are typically 7 k; CC

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 11 of 32 initialization noted under “Reset,” bit 6 of the Processor Statusand Control Register is set to “1” to indicate to the firmwarethat a Watch Dog Reset occurred. The Watch Dog Timer is a 2-bit timer clocked by a 4.096-msclock (b...

Page 13 - DAC Port

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 13 of 32 In “Resistive” mode, a 7-k Ω pull-up resistor is conditionally enabled for all pins of a GPIO port. The resistor is enabled forany pin that has been written as a “1.” The resistor is disabledon any pin that has been written as...

Page 16 - USB Device; Table

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 16 of 32 The Bus Activity bit is a “sticky” bit that indicates if any non-idleUSB event has occurred on the USB bus. The user firmwareshould check and clear this bit periodically to detect any lossof bus activity. Writing a “0” to the ...

Page 18 - Processor Status and Control Register; Table 22.Timer Register

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 18 of 32 12-bit Free-running Timer The 12-bit timer provides two interrupts (128 µ s and 1.024 ms) and allows the firmware to directly time events that are up to4 ms in duration. The lower 8 bits of the timer can be readdirectly by the...

Page 19 - Interrupts; Table 25.Global Interrupt Enable Register

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 19 of 32 The “Single Step” (bit 1) is provided to support a hardwaredebugger. When single step is set, the processor will executeone instruction and halt (clear the run bit). This bit must becleared for normal operation. The “Interrupt...

Page 21 - Truth Tables; Table 28.USB Register Mode Encoding

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 21 of 32 Truth Tables The ‘In’ column represents the SIE’s response to the tokentype. A disabled endpoint will remain such until firmware changes it,and all endpoints reset to disabled. Any Setup packet to an enabled and accepting endp...

Page 26 - Switching Characteristics

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 26 of 32 Notes: 9. Per Table 7-7 of revision 1.1 of USB specification, for C LOAD of 50–600 pF. 10. Measured as largest step size vs. nominal according to measured full scale and zero programmed values. 11. T ratio = Isink1[1:0](n)/Isi...

Page 27 - Figure 8. Clock Timing; CLOCK; Figure 9. USB Data Signal Timing; Paired; Consecutive

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 27 of 32 . Figure 8. Clock Timing CLOCK t CYC t CL t CH Figure 9. USB Data Signal Timing Figure 10. Receiver Jitter Tolerance 90% 10% 90% 10% D − D + t r t f V crs V oh V ol Differential Data Lines Paired Transitions N * T PERIOD + T J...

Page 28 - Ordering Information

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 28 of 32 Figure 11. Differential to EOP Transition Skew and EOP Width Figure 12. Differential Data Jitter T PERIOD Differential Data Lines Crossover Point Crossover Point Extended Source EOP Width: T EOPT Receiver EOP Width: T EOPR1 , ...

Page 29 - Die Pad Locations; Pin Name; XtalOut; XtalIn

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 29 of 32 Die Pad Locations Table 30.DIe Pad Locations (in microns) Pad # Pin Name X Y Pad # Pin Name X Y 1 D+ 1496.95 2995.00 48 V CC 1619.65 3023.60 2 D- 467.40 2995.00 47 V SS 1719.65 3023.60 3 Port3[7] 345.15 3023.60 46 Port3[6] 182...

Page 30 - Package Diagrams; 8-Lead Shrunk Small Outline Package SP48

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 30 of 32 Package Diagrams 48-Lead Shrunk Small Outline Package SP48 51-85061-*C 51-85019-*A 40-Lead (600-Mil) Molded DIP P2 [+] Feedback

Page 31 - PIN 1 ID

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 31 of 32 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embo...

Page 32 - Document History Page; Issue

CY7C63413CCY7C63513CCY7C63613C Document #: 38-08027 Rev. *B Page 32 of 32 Document History Page Document Title: CY7C63413C, CY7C63513C, CY7C63613C Low-speed High I/O, 1.5 -Mbps USB ControllerDocument Number: 38-08027 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 116224 06/12/02 DS...