Page 2 - Logic Block Diagram
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 2 of 83 Internal 24 MHz Oscillator 3.3V Regulator Clock Control POR / Low-Voltage Detect Watchdog Timer RAM Up to 256 Byte M8C CPU Flash Up to 8K Byte Up to 14 Extended IO Pins Low-Speed USB/PS2 Transceiver and Pull up Up to 6 GPIO pins Wakeup Time...
Page 4 - Top View
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 4 of 83 5. Pinouts Figure 5-1. Pin Diagrams 123456 9 11 15 16 17 18 19 20 2221 NC P0.7 TIO1/P0.6TIO0/P0.5 INT2/P0.4INT1/P0.3 P0.0 P2.0 P1.5/SMOSI P1.3/SSEL P3.1P3.0 V CC P1.2/VREG P1.1/D–P1.0/D+ 14 P1.4/SCLK 10 P2.1 NC V SS 12 13 78 INT0/P0.2 P0.1 ...
Page 5 - Legend; Pad Number; VSS
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 5 of 83 Figure 5-2. CY7C63823 Die Form Die step = 1792 .98 μ m x 22 72.998 μ m Die si ze = 1727 μ m x 2187 μ m Bon d pad op enin g = 70 μ m x 70 μ m Die thic kn ess = 14 mils Legend 1 2 4 3 5 6 8 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Cypres...
Page 9 - Addressing Modes; Examples
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 9 of 83 7.2 Addressing Modes 7.2.1 Source Immediate The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. Opera...
Page 12 - Instruction Set Summary; The instruction set is summarized in
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 12 of 83 8. Instruction Set Summary The instruction set is summarized in Table 8-1 numerically and serves as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly ...
Page 13 - Memory Organization; Flash Program Memory Organization; Figure 9-1. Program Memory Space with Interrupt Vector Table
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 13 of 83 9. Memory Organization 9.1 Flash Program Memory Organization Figure 9-1. Program Memory Space with Interrupt Vector Table after reset Address 16-bit PC 0x0000 Program execution begins here after a reset 0x0004 POR/LVD 0x0008 INT0 0x000C SP...
Page 14 - Data Memory Organization; SROM; Stack begins here and grows upward.
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 14 of 83 9.2 Data Memory Organization The CY7C63310/638xx microcontrollers provide up to 256 bytes of data RAM. 9.3 Flash This section describes the Flash block of the enCoRe II. Much of the user visible Flash functionality including programming an...
Page 15 - SROM Function Descriptions
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 15 of 83 Two important variables that are used for all functions are KEY1 and KEY2. These variables are used to help discriminate between valid SSCs and inadvertent SSCs. KEY1 must always have a value of 3Ah, while KEY2 must have the same value as ...
Page 19 - Stack Pointer value when SSC is
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 19 of 83 9.5.8 Checksum Function The Checksum function calculates a 16-bit checksum over a user specifiable number of blocks, within a single Flash macro (Bank) starting from block zero. The BLOCKID parameter is used to pass in the number of blocks...
Page 21 - Clock Architecture Description
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 21 of 83 10.1 Clock Architecture Description The enCoRe II clock selection circuitry allows the selection of independent clocks for the CPU, USB, Interval Timers and Capture Timers. The CPU clock CPUCLK is sourced from an external clock or the Inte...
Page 22 - Proper USB SIE operation requires a 12 MHz or 24 MHz
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 22 of 83 Table 10-2. LPOSC Trim (LPOSCTR) [0x36] [R/W] Bit # 7 6 5 4 3 2 1 0 Field 32 kHz Low Power Reserved 32 kHz Bias Trim [1:0] 32 kHz Freq Trim [3:0] Read/Write R/W – R/W R/W R/W R/W R/W R/W Default 0 D D D D D D D This register is used to cal...
Page 25 - Figure 10-2. Programmable Interval Timer Block Diagram
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 25 of 83 10.1.1 Interval Timer Clock (ITMRCLK) The Interval Timer Clock (TITMRCLK), is sourced from an external clock, the Internal 24 MHz Oscillator, the Internal 32 kHz Low power Oscillator, or the Timer Capture clock. A programmable prescaler of...
Page 26 - CPU Clock During Sleep Mode; on page 22) is forced to the Internal Oscillator, and the; Figure 10-3. Timer Capture Block Diagram
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 26 of 83 10.2 CPU Clock During Sleep Mode When the CPU enters sleep mode the CPUCLK Select (Bit [0], Table 10-3 on page 22) is forced to the Internal Oscillator, and the oscillator is stopped. When the CPU comes out of sleep mode it runs on the int...
Page 27 - Sleep Mode
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 27 of 83 11. Reset The microcontroller supports two types of resets: Power on Reset (POR) and Watchdog Reset (WDR). When reset is initiated, all registers are restored to their default states and all interrupts are disabled.The occurrence of a rese...
Page 28 - Watchdog Timer Reset
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 28 of 83 11.1 Power on Reset POR occurs every time the power to the device is switched on. POR is released when the supply is typically 2.6V for the upward supply transition, with typically 50 mV of hysteresis during the power on transient. Bit 4 o...
Page 29 - Wake up Sequence
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 29 of 83 12.1 Sleep Sequence The SLEEP bit is an input into the sleep logic circuit. This circuit is designed to sequence the device into and out of the hardware sleep state. The hardware sequence to put the device to sleep is shown in Figure 12-1....
Page 30 - Low Power in Sleep Mode
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 30 of 83 12.3 Low Power in Sleep Mode To achieve the lowest possible power consumption during suspend or sleep, the following conditions must be observed in addition to considerations for the sleep timer: 1. All GPIOs must be set to outputs and dri...
Page 31 - Low Voltage Detect Control
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 31 of 83 13. Low Voltage Detect Control Table 13-1. Low Voltage Control Register (LVDCR) [0x1E3] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Reserved PORLEV[1:0] Reserved VM[2:0] Read/Write – – R/W R/W – R/W R/W R/W Default 0 0 0 0 0 0 0 0 This register cont...
Page 32 - ators
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 32 of 83 13.0.1 ECO Trim Register Table 13-2. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R] Bit # 7 6 5 4 3 2 1 0 Field Reserved LVD PPOR Read/Write – – – – – – R R Default 0 0 0 0 0 0 0 0 This read only register allows reading the curr...
Page 33 - Port Data Registers; from this register returns the current state of the Port 0 pins.
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 33 of 83 14. General Purpose IO (GPIO) Ports 14.1 Port Data Registers Table 14-1. P0 Data Register (P0DATA)[0x00] [R/W] Bit # 7 6 5 4 3 2 1 0 Field P0.7 P0.6/TIO1 P0.5/TIO0 P0.4/INT2 P0.3/INT1 P0.2/INT0 P0.1/CLKOUT P0.0/CLKIN Read/Write R/W R/W R/W...
Page 35 - GPIO Port Configuration
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 35 of 83 14.2 GPIO Port Configuration All the GPIO configuration registers have common configuration controls. The following are the bit definitions of the GPIO configuration registers. 14.2.1 Int Enable When set, the Int Enable bit allows the GPIO...
Page 36 - CLK Output
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 36 of 83 Figure 14-1. Block Diagram of a GPIO V CC VREG V CC VREG GPIO PIN R UP Data Out V CC GND VREG GND 3.3V Drive Pull-Up Enable Output Enable Open Drain Port Data High Sink Data In TTL Threshold Table 14-5. P0.0/CLKIN Configuration (P00CR) [0x...
Page 37 - on page 55 and; interrupt sources, it is best to follow the following procedure:
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 37 of 83 Table 14-7. P0.2/INT0–P0.4/INT2 Configuration (P02CR–P04CR) [0x07–0x09] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Reserved Int Act Low TTL Thresh Reserved Open Drain Pull up Enable Output Enable Read/Write – – R/W R/W – R/W R/W R/W Default 0 0 0 0...
Page 38 - DC Characteristics
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 38 of 83 Table 14-9. P0.7 Configuration (P07CR) [0x0C] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Reserved Int Enable Int Act Low TTL Thresh Reserved Open Drain Pull up Enable Output Enable Read/Write – R/W R/W R/W – R/W R/W R/W Default 0 0 0 0 0 0 0 0 This...
Page 39 - Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 39 of 83 Table 14-13. P1.3 Configuration (P13CR) [0x10] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Reserved Int Enable Int Act Low 3.3V Drive High Sink Open Drain Pull up Enable Output Enable Read/Write – R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 ...
Page 40 - SPI Data Register; meet this timing requirement results in incorrect data transfer.
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 40 of 83 15. Serial Peripheral Interface (SPI) The SPI Master/Slave Interface core logic runs on the SPI clock domain, so that its functionality is independent of system clock speed. SPI is a four pin serial interface comprised of a clock, an enabl...
Page 41 - SPI Configure Register; Note for Comm Modes 01b or 10b (SPI Master or SPI Slave); SCLK Frequency when CPUCLK =
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 41 of 83 15.2 SPI Configure Register Table 15-2. SPI Configure Register (SPICR) [0x3D] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Swap LSB First Comm Mode CPOL CPHA SCLK Select Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit 7: Swap 0...
Page 42 - SPI Interface Pins; LSB First CPHA CPOL
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 42 of 83 15.3 SPI Interface Pins The SPI interface uses the P1.3–P1.6 pins. These pins are configured using the P1.3 and P1.4–P1.6 Configuration. Table 15-4. SPI Mode Timing vs. LSB First, CPOL and CPHA LSB First CPHA CPOL Diagram 0 0 0 0 0 1 0 1 0...
Page 43 - s rate; order byte must be written first then the high order byte.
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 43 of 83 16. Timer Registers All timer functions of the enCoRe II are provided by a single timer block. The timer block is asynchronous from the CPU clock. 16.1 Registers 16.1.1 Free Running Counter The 16 bit free-running counter is clocked by the...
Page 45 - Figure 16-2. Programmable Interval Timer Block Diagram
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 45 of 83 Table 16-8. Programmable Interval Timer High (PITMRH) [0x27] [R] Bit # 7 6 5 4 3 2 1 0 Field Reserved Prog Interval Timer [11:8] Read/Write – – – – R R R R Default 0 0 0 0 0 0 0 0 Bit [7:4]: Reserved Bit [3:0]: Prog Internal Timer [11:8] T...
Page 46 - First Edge Hold
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 46 of 83 16.1.2 Timer Capture Cypress enCoRe II has two 8-bit captures. Each capture has separate registers for the rising and falling time. The two eight bit captures can be configured as a single 16-bit capture. When configured, the capture 1 reg...
Page 48 - Figure 16-3. Timer Functional Sequence Diagram
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 48 of 83 Figure 16-3. Timer Functional Sequence Diagram [+] Feedback [+] Feedback
Page 49 - Valid
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 49 of 83 Figure 16-4. 16-Bit Free Running Counter Loading Timing Diagram clk_sys write valid addr write data FRT reload ready Clk Timer 12b Prog Timer 12b reload interrupt Capture timer clk 16b free running counter load 16b free running counter 00A...
Page 50 - Interrupt Controller; Architectural Description; Interrupt
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 50 of 83 17. Interrupt Controller The interrupt controller and its associated registers allow the user’s code to respond to an interrupt from almost every functional block in the enCoRe II devices. The registers associated with the interrupt contro...
Page 51 - Figure 17-1. Interrupt Controller Block Diagram; I n ter r u p t
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 51 of 83 17.2 Interrupt Processing The sequence of events that occur during interrupt processing follows: 1. An interrupt becomes active, because: a. The interrupt condition occurs (for example, a timer expires).b. A previously posted interrupt is ...
Page 52 - Interrupt Registers
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 52 of 83 17.5 Interrupt Registers The Interrupt Clear Registers (INT_CLRx) are used to enable the individual interrupt sources’ ability to clear posted interrupts.When an INT_CLRx register is read, any bits that are set indicates an interrupt has b...
Page 56 - Regulator Output; This block must not be enabled when V; the alternate voltage.
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 56 of 83 18. Regulator Output 18.1 VREG Control Table 18-1. VREG Control Register (VREGCR) [0x73] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Reserved Keep Alive VREG Enable Read/Write – – – – – – R/W R/W Default 0 0 0 0 0 0 0 0 Bit [7:2]: Reserved Bit 1: Ke...
Page 57 - USB Transceiver Configuration
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 57 of 83 19. USB/PS2 Transceiver Although the USB transceiver has features to assist in interfacing to PS/2, these features are not controlled using these registers. The registers only control the USB interfacing features. PS/2 interfacing options ...
Page 58 - USB Device Address; USB Enable
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 58 of 83 21. USB Device 21.1 USB Device Address 21.2 Endpoint 0, 1, and 2 Count Table 21-1. USB Device Address (USBCR) [0x40] [R/W] Bit # 7 6 5 4 3 2 1 0 Field USB Enable Device Address[6:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 ...
Page 59 - SETUP Received
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 59 of 83 21.3 Endpoint 0 Mode Because both firmware and the SIE are allowed to write to the Endpoint 0 Mode and Count Registers, the SIE provides an interlocking mechanism to prevent accidental overwriting of data.When the SIE writes to these regis...
Page 61 - Encoding Column
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 61 of 83 The three data buffers are used to hold data for both IN and OUT transactions. Each data buffer is 8 bytes long.The reset values of the Endpoint Data Registers are unknown.Unlike past enCoRe parts the USB data buffers are only accessible i...
Page 62 - Endpoint Count Register (; Details of Mode for Differing Traffic Conditions
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 62 of 83 22.3 SETUP, IN, and OUT Columns Depending on the mode specified in the 'Encoding' column, the 'SETUP', 'IN', and 'OUT' columns contain the SIE's responses when the endpoint receives SETUP, IN, and OUT tokens, respectively. A 'Check' in the...
Page 65 - Register Summary
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 65 of 83 2A TMRCR First Edge Hold 8-bit capture Prescale Cap0 16bit Enable Reserved bbbbb--- 00000000 2B TCAPINTE Reserved Cap1 Fall Active Cap1 Rise Active Cap0 Fall Active Cap0 Rise Active ----bbbb 00000000 2C TCAPINTS Reserved Cap1 Fall Active C...
Page 67 - Voltage Vs CPU Frequency Characteristics; Figure 25-1. Voltage vs CPU Frequency Characteristics
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 67 of 83 25. Voltage Vs CPU Frequency Characteristics Figure 25-1. Voltage vs CPU Frequency Characteristics Running the CPU at 24 MHz requires a minimum voltage of 4.75V. This applies to any CPU speed above 12 MHz, so using an external clock betwee...
Page 70 - AC Characteristics
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 70 of 83 USB Driver T R1 Transition Rise Time C LOAD = 200 pF 75 ns T R2 Transition Rise Time C LOAD = 600 pF 300 ns T F1 Transition Fall Time C LOAD = 200 pF 75 ns T F2 Transition Fall Time C LOAD = 600 pF 300 ns T R Rise/Fall Time Matching 80 125...
Page 71 - GPIO Pin Output; Paired; Consecutive
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 71 of 83 1 Figure 28-2. GPIO Timing Diagram Figure 28-1. Clock Timing Figure 28-3. USB Data Signal Timing CLOCK T CYC T CL T CH 10% T R_GPIO T F_GPIO GPIO Pin Output Voltage 90% 90% 10% 90% 10% D − D + T R T F V crs V oh V ol Figure 28-4. Receiver ...
Page 72 - Figure 28-5. Differential to EOP Transition Skew and EOP Width
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 72 of 83 Figure 28-5. Differential to EOP Transition Skew and EOP Width T PERIOD Differential Data Lines Crossover Point Crossover Point Extended Source EOP Width: T EOPT Receiver EOP Width: T EOPR1 , T EOPR2 Diff. Data to SE0 Skew N * T PERIOD + T...
Page 76 - Package Diagrams; DIMENSIONS IN INCHES
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 76 of 83 31. Package Diagrams Figure 31-1. 16-Pin (300-Mil) Molded DIP P1 Figure 31-2. 16-Pin (150-Mil) SOIC S16.15 DIMENSIONS IN INCHES MIN. MAX. SEATING PLANE 0.240 0.260 0.015 0.035 0.740 0.770 0.120 0.140 0.015 0.060 0.015 0.020 0.055 0.065 0.1...
Page 77 - REFERENCE JEDEC MO-119
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 77 of 83 Figure 31-3. 18-Pin (300-Mil) Molded DIP P3 Figure 31-4. 18-Pin (300-Mil) Molded SOIC S3 DIMENSIONS IN INCHES MIN. MAX. SEATING PLANE 0.240 0.270 0.030 0.060 0.870 0.920 0.140 0.190 0.090 0.110 0.055 0.065 0.015 0.020 0.120 0.140 0.015 0.0...
Page 80 - Document History Page; II Low Speed USB Peripheral Controller
CY7C63310, CY7C638xx Document 38-08035 Rev. *K Page 80 of 83 32. Document History Page Document Title: CY7C63310, CY7C638xx enCoRe ™ II Low Speed USB Peripheral Controller Document Number: 38-08035 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 131323 XGR 12/11/03 New data she...
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