Cypress CY7C601xx - Manuals

Page 3 - Top View

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 3 of 68 6. Pinouts Figure 6-1. Package Configurations 123456 9 11 15 16 17 18 19 20 2221 NC P0.7 TIO1/P0.6TIO0/P0.5 INT2/P0.4INT1/P0.3 CLKIN\P0.0 P2.0 P1.5/SMOSI P1.3/SSEL P3.1P3.0 V DD P1.2 P1.1P1.0 14 P1.4/SCLK 10 P2.1 NC V SS 12 13 78 INT0/P0.2 ...

Page 7 - Note; b = Both Read and Write; Table 7-1. enCoRe II LV Register Summary

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 7 of 68 Note In the R/W column: b = Both Read and Write r = Read Only w = Write Only c = Read or Clear d = Calibration Value. Must not change during normal use 34 IOSCTR foffset[2:0] Gain[4:0] bbbbbbbb 000ddddd 35 XOSCTR Reserved XOSC XGM [2:0] Res...

Page 10 - Addressing Modes

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 10 of 68 9.2 Addressing Modes 9.2.1 Source Immediate The result of an instruction using this addressing mode is placedin the A register, the F register, the SP register, or the X register,which is specified as part of the instruction opcode. Operan...

Page 12 - Instruction Set Summary; PSoC Designer Assembly Language User Guide

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 12 of 68 9.2.9 Source Indirect Post Increment The result of an instruction using this addressing mode is placedin the Accumulator. Operand 1 is an address pointing to alocation within the memory space, which contains an address(the indirect address...

Page 14 - Memory Organization; Flash Program Memory Organization; Figure 11-1. Program Memory Space with Interrupt Vector Table

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 14 of 68 11. Memory Organization 11.1 Flash Program Memory Organization Figure 11-1. Program Memory Space with Interrupt Vector Table after reset Address 16-bit PC 0x0000 Program execution begins here after a reset 0x0004 POR/LVD 0x0008 INT0 0x000C...

Page 15 - Data Memory Organization; parameter block; Stack begins here and grows upward

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 15 of 68 11.2 Data Memory Organization The CY7C601xx and CY7C602xx microcontrollers provide up to 256 bytes of data RAM Figure 11-2. Data Memory Organization 11.3 Flash This section describes the Flash block of enCoRe II LV. Much ofthe visible Flas...

Page 16 - SROM Function Descriptions

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 16 of 68 Two important variables used for all functions are KEY1 andKEY2. These variables help discriminate between valid andinadvertent SSCs. KEY1 always has a value of 3Ah, while KEY2has the same value as the stack pointer when the SROMfunction b...

Page 17 - Clocking

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 17 of 68 11.5.3 WriteBlock Function The WriteBlock function is used to store data in Flash. Data ismoved 64 bytes at a time from SRAM to Flash using this function.The WriteBlock function first checks the protection bits and deter-mines if the desir...

Page 19 - SROM Table Read Description; SROM

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 19 of 68 11.6 SROM Table Read Description The Silicon IDs for enCoRe II LV devices are stored in SROM tables in the part, as shown in Figure 11-3. on page 20 The Silicon ID can be read out from the part using SROM Table reads. This is demonstrated ...

Page 20 - BLOCKID

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 20 of 68 Figure 11-3. SROM Table 11.6.1 Checksum Function The Checksum function calculates a 16-bit checksum over auser specifiable number of blocks, within a single Flash macro(Bank) starting from block zero. The BLOCKID parameter isused to pass i...

Page 21 - Trim Values for the IOSCTR Register; SROM Table Read Description; Supervisory ROM Table

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 21 of 68 12. Clocking The enCoRe II LV has two internal oscillators, the internal 24MHz oscillator and the 32 kHz low power oscillator. The internal 24 MHz oscillator is designed such that it is trimmedto an output frequency of 24 MHz over temperat...

Page 22 - Clock Architecture Description; where

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 22 of 68 When using the 32 kHz oscillator, the PITMRL/H is read until twoconsecutive readings match before sending and receiving data.The following firmware example assumes the developer isinterested in the lower byte of the PIT. Read_PIT_counter:m...

Page 23 - Reserved; The CPU speed selection is configured using the OSC_CR0 Register (

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 23 of 68 Figure 12-1. CPU Clock Block Diagram SCALE (divide by 2 n, n = 0-5,7) MUX CLK_EXT CLK_24MHz CPUCLK SEL CLK_CPU Doubler CLK_HS LP OSC 32-KHz CLK_32KHz XTAL OSC 1-24MHz CY7C601xx only MUX Crystal Oscillator Disabled XOSC SEL EN CLK_EXT EFTB ...

Page 28 - Resonator

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 28 of 68 12.2.4 Internal Clock Trim 12.2.5 External Clock Trim Table 12-6. IOSC Trim (IOSCTR) [0x34] [R/W] Bit # 7 6 5 4 3 2 1 0 Field foffset[2:0] Gain[4:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 D D D D D The IOSC Calibrate Regi...

Page 29 - CPU Clock During Sleep Mode; When the CPU enters sleep mode the CPUCLK Select (Bit 0,; 2 kHz Low Power; conditions with this setting.

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 29 of 68 12.2.6 LPOSC Trim 12.3 CPU Clock During Sleep Mode When the CPU enters sleep mode the CPUCLK Select (Bit 0, Table 12-2 ) is forced to the internal oscillator, and the oscillator is stopped. When the CPU comes out of sleep mode it runs on t...

Page 30 - Sleep Mode

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 30 of 68 13. Reset The microcontroller supports two types of resets: Power on Reset (POR) and Watchdog Reset (WDR). When reset is initiated, allregisters are restored to their default states and all interrupts are disabled. The occurrence of a rese...

Page 31 - Watchdog Timer Reset

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 31 of 68 13.1 Power On Reset POR occurs every time the power to the device is switched on.POR is released when the supply is typically 2.6V for the upwardsupply transition, with typically 50 mV of hysteresis during thepower on transient. Bit 4 of t...

Page 33 - Wakeup Sequence

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 33 of 68 14.2 Wakeup Sequence When asleep, the only event that wakes the system up is aninterrupt. The global interrupt enable of the CPU flag registerneed not be set. Any unmasked interrupt wakes the system up.It is optional for the CPU to actuall...

Page 34 - Low Voltage Detect Control

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 34 of 68 15. Low Voltage Detect Control Table 15-1. Low Voltage Control Register (LVDCR) [0x1E3] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Reserved PORLEV[1:0] Reserved VM[2:0] Read/Write – – R/W R/W – R/W R/W R/W Default 0 0 0 0 0 0 0 0 This register cont...

Page 36 - General Purpose IO Ports; Port Data Registers

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 36 of 68 16. General Purpose IO Ports 16.1 Port Data Registers 16.1.1 P0 Data 16.1.2 P1 Data Table 16-1. P0 Data Register (P0DATA)[0x00] [R/W] Bit # 7 6 5 4 3 2 1 0 Field P0.7 P0.6/TIO1 P0.5/TIO0 P0.4/INT2 P0.3/INT1 P0.2/INT0 P0.1/CLKOUT P0.0/CLKIN...

Page 37 - GPIO Port Configuration; When clear, the corresponding interrupt is disabled on the pin.; The GPIOs default to CMOS threshold. User’s firmware

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 37 of 68 16.1.3 P2 Data 16.1.4 P3 Data 16.1.5 P4 Data 16.2 GPIO Port Configuration All GPIO configuration registers have common configurationcontrols. By default all GPIOs are configured as inputs. Toprevent the inputs from floating, pull up resist...

Page 39 - CLK Output; and; follow this procedure:

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 39 of 68 16.2.10 P0.1/CLKOUT Configuration 16.2.11 P0.2/INT0–P0.4/INT2 Configuration Table 16-7. P0.1/CLKOUT Configuration (P01CR) [0x06] R/W] Bit # 7 6 5 4 3 2 1 0 Field CLK Output Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull up Ena...

Page 40 - DC Characteristics

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 40 of 68 16.2.12 P0.5/TIO0–P0.6/TIO1 Configuration 16.2.13 P0.7 Configuration 16.2.14 P1.0 Configuration Table 16-9. P0.5/TIO0–P0.6/TIO1 Configuration (P05CR–P06CR) [0x0A–0x0B] [R/W] Bit # 7 6 5 4 3 2 1 0 Field TIO Output Int Enable Int Act Low TTL...

Page 42 - Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 42 of 68 16.2.18 P1.4–P1.6 Configuration (SCLK, SMOSI, SMISO) 16.2.19 P1.7 Configuration 16.2.20 P2 Configuration Table 16-15. P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W] Bit # 7 6 5 4 3 2 1 0 Field SPI Use Int Enable Int Act Low Reserv...

Page 45 - Important Note for Comm Modes 01b or 10b (SPI Master or SPI Slave)

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 45 of 68 17.1 SPI Data Register When an interrupt occurs to indicate to firmware that a byte of receive data is available or the transmitter holding register is empty,firmware has seven SPI clocks to manage the buffers—to empty the receiver buffer ...

Page 47 - SPI Interface Pins; SCLK

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 47 of 68 17.3 SPI Interface Pins The SPI interface uses the P1.3–P1.6 pins. These pins are configured using the P1.3 and P1.4–P1.6 configuration. 18. Timer Registers All timer functions of the enCoRe II LV are provided by a single timer block. The ...

Page 48 - Figure 18-2. Time Capture Block Diagram; First Edge Hold

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 48 of 68 18.1.2 Time Capture enCoRe II LV has two 8-bit captures. Each capture has a separate register for rising and falling time. The two 8-bit captures can beconfigured as a single 16-bit capture. When configured in this way, the capture 1 regis...

Page 52 - Figure 18-3. Timer Functional Sequence Diagram

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 52 of 68 Figure 18-3. Timer Functional Sequence Diagram [+] Feedback [+] Feedback

Page 53 - Memory mapped registers Read/Write timing diagram

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 53 of 68 Figure 18-4. 16-Bit Free Running Counter Loading Timing Diagram Figure 18-5. Memory Mapped Registers Read and Write Timing Diagram clk_sys write valid addr write data FRT reload ready Clk Timer 12b Prog Timer 12b reload interrupt Capture t...

Page 54 - Interrupt Controller; Architectural Description; I n ter r u p t

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 54 of 68 19. Interrupt Controller The interrupt controller and its associated registers allow theuser’s code to respond to an interrupt from almost everyfunctional block in the enCoRe II LV devices. The registersassociated with the interrupt contro...

Page 59 - Absolute Maximum Ratings; DC Characteristics

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 59 of 68 20. Absolute Maximum Ratings Storage Temperature ................................... –40°C to +90°C Ambient Temperature with Power Applied..... –0°C to +70°C Supply Voltage on V CC Relative to V SS ..........–0.5V to +7.0V DC Input Voltage...

Page 60 - AC Characteristics

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 60 of 68 Figure 20-1. Clock Timing 20.2 AC Characteristics Parameter Description Conditions Min Typical Max Unit Clock T ECLKDC External Clock Duty Cycle 45 55 % T ECLK2 External Clock Frequency 1 24 MHz F IMO Internal Main Oscillator Frequency Wit...

Page 61 - SS

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 61 of 68 Figure 20-2. GPIO Timing Diagram Figure 20-3. SPI Master Timing, CPHA = 1 10% T R_GPIO T F_GPIO GPIO Pin Output Voltage 90% MSB T MSU LSB T MHD T SCKH T MDO SS SCK (CPOL=0) SCK (CPOL=1) MOSI MISO (SS is under firmware control in SPI Master...

Page 63 - Ordering Information; Bake Temperature

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 63 of 68 Figure 20-6. SPI Slave Timing, CPHA = 0 1 MSB T SSU LSB T SHD T SCKH T SDO1 SS SCK (CPOL=0) SCK (CPOL=1) MOSI MISO T SCKL T SDO LSB MSB T SSS T SSH 21. Ordering Information Ordering Code FLASH Size RAM Size Package Type CY7C60123-PVXC 8K 2...

Page 64 - Package Diagrams

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 64 of 68 23. Package Diagrams Figure 23-1. 24-Pin (300-Mil) SOIC S13 Figure 23-2. 24-Pin (300-Mil) PDIP P13 PIN 1 ID SEATING PLANE 0.597[15.163] 0.615[15.621] 1 12 13 24 * * * 0.291[7.391]0.300[7.620] 0.394[10.007]0.419[10.642] 0.050[1.270] TYP. 0....

Page 67 - Document History Page

CY7C601xx, CY7C602xx Document 38-16016 Rev. *E Page 67 of 68 24. Document History Page Document Title: CY7C601xx, CY7C602xx enCoRe ™ II Low Voltage Microcontroller Document Number: 38-16016 Rev. ECN Orig. of Change Submission Date Description of Change ** 327601 BON See ECN New data sheet *A 400134 ...