Cypress CY7C2563KV18 - Manuals

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 7 of 29 K Input Clock Positive Input Clock Input . The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q [x:0] . All accesses are initiated on t...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 8 of 29 Functional Overview The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18,CY7C2565KV18 are synchronous pipelined Burst SRAMsequipped with a read port and a write port. The read port isdedicated to...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 9 of 29 Read access and write access must be scheduled such that onetransaction is initiated on any clock cycle. If both ports areselected on the same K clock rise, the arbitration depends on the...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 10 of 29 Application Example Figure 1 shows two QDR-II+ used in an application. Figure 1. Application Example Table 3. Truth Table The truth table for CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, an...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 13 of 29 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 15 of 29 Figure 2. TAP Controller State Diagram The state diagram for the TAP controller follows. [13] TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 16 of 29 Figure 3. TAP Controller Block Diagram TAP Electrical Characteristics Over the Operating Range [14, 15, 16] Parameter Description Test Conditions Min Max Unit V OH1 Output HIGH Voltage I...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 17 of 29 TAP AC Switching Characteristics Over the Operating Range [17, 18] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIG...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 19 of 29 Table 10. Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N ...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 20 of 29 Power Up Sequence in QDR-II+ SRAM QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF ...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 21 of 29 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................. –65°C to +1...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 22 of 29 I SB1 Automatic Power down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL f = f MAX = 1/t CYC , Inputs Static 550 MHz (x8) 380 mA (x9) 380 (x18) 380 (x36) 380 500 M...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 23 of 29 AC Test Loads and Waveforms 1.25V 0.25V R = 50 Ω 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES Device R L = 50 Ω Z 0 = 50 Ω V REF = 0.75V V REF = 0.75V [24] 0.75V Under Test 0.75V Device...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 25 of 29 Switching Waveforms Read/Write/Deselect Sequence [32, 33, 34] Figure 6. Waveform for 2.5 Cycle Read Latency t KH t KL t CYC t KHKH t t t tSA HA SC HC t HD tSC tHC A0 A1 A2 A3 t t SD HD t...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 26 of 29 Ordering Information The following table lists all possible speed, package and temperature range options supported for these devices. Note that some options listed may not be available f...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 27 of 29 450 CY7C2561KV18-450BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C2576KV18-450BZCCY7C2563KV18-450BZCCY7C2565KV18-450BZCCY7C2561KV18-450BZXC 51-85180 ...

PRELIMINARY CY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 28 of 29 Package Diagram Figure 7. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING ...

Document Number: 001-15887 Rev. *E Revised April 24, 2009 Page 29 of 29 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this documentare the trademarks of their respective holders. PRE...