Cypress CY7C1546V18 - Manuals

Cypress CY7C1546V18 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1546V18

Summary

Page 2 - Array; Array

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 2 of 28 Logic Block Diagram (CY7C1546V18) Logic Block Diagram (CY7C1557V18) CLK A (21:0) Gen. K K Control Logic Address Register R ead Add. Decode Read Data Reg. R/W DQ [7:0] Output Logic Reg. Reg. Reg. 8 8 16 8...

Page 3 - ray

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 3 of 28 Logic Block Diagram (CY7C1548V18) Logic Block Diagram (CY7C1550V18) CLK A (20:0) Gen. K K Control Logic Address Register R ead Add. Decode Read Data Reg. R/W DQ [17:0] Output Logic Reg. Reg. Reg. 18 18 3...

Page 4 - Pin Configuration

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 4 of 28 Pin Configuration The pin configuration for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follow. [2] 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1546V18 (8M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ A ...

Page 6 - Pin Definitions; Switching Characteristics

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 6 of 28 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input and Output Synchronous Data Input or Output Signals . Inputs are sampled on the rising edge of K and K clocks during valid write operations. The...

Page 8 - Functional Overview; Write Operations

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 8 of 28 Functional Overview The CY7C1546V18, CY7C1557V18, CY7C1548V18, andCY7C1550V18 are synchronous pipelined Burst SRAMsequipped with a DDR interface. Accesses are initiated on the rising edge of the positive...

Page 9 - Echo Clocks; DLL; Application Example; Figure 1; Figure 1. Application Example; BUS; DQ

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 9 of 28 Echo Clocks Echo clocks are provided on the DDR-II+ to simplify data captureon high-speed systems. Two echo clocks are generated by theDDR-II+. CQ is referenced with respect to K and CQ is refer-enced wi...

Page 10 - Truth Table

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 10 of 28 Truth Table The truth table for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follows. [3, 4, 5, 6, 7, 8] Operation K LD R/W DQ DQ Write Cycle:Load address; wait one cycle; input write data on ...

Page 12 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 12 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test AccessPort (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-2001. The TAP ope...

Page 13 - and t; ). The SRAM clock input might not be captured

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 13 of 28 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO pins and shifts the IDCODE out of thedevic...

Page 14 - TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 14 of 28 TAP Controller State Diagram The state diagram for the TAP controller follows. [10] TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1 0 1 ...

Page 18 - Boundary Scan Order; Internal

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 18 of 28 Boundary Scan Order Bit Number Bump ID Bit Number Bump ID Bit Number Bump ID Bit Number Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F ...

Page 19 - Power Up Waveforms; Figure 3. Power Up Waveforms; DOFF; Unstable Clock

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 19 of 28 Power Up Sequence in DDR-II+ SRAM DDR-II+ SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. Duringpower up, when the DOFF is tied HIGH, the DLL is locked af...

Page 20 - Maximum Ratings; Operating Range; DC Electrical Characteristics

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 20 of 28 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Tem...

Page 21 - AC Electrical Characteristics; Capacitance

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 21 of 28 I SB1 Automatic Power down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL f = f MAX = 1/t CYC , Inputs Static 375MHz (x8) 525 mA (x9) 525 (x18) 525 (x36) 525 333MHz (x8) 500 mA (x9...

Page 22 - Figure 4. AC Test Loads and Waveforms; ZQ

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 22 of 28 AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms 1.25V 0.25V R = 50 Ω 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES Device R L = 50 Ω Z 0 = 50 Ω V REF = 0.75V V REF = 0.75V [21] 0.75V U...

Page 24 - Switching Waveforms; Figure 5. Waveform for 2.0 Cycle Read Latency; DON’T CARE; t CQD

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 24 of 28 Switching Waveforms Read/Write/Deselect Sequence [29, 30, 31, 32] Figure 5. Waveform for 2.0 Cycle Read Latency DON’T CARE UNDEFINED 1 2 3 4 5 6 7 8 9 10 READ READ READ NOP WRITE WRITE t NOP 11 K K LD R...

Page 25 - Ordering Information; for actual products offered.

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 25 of 28 Ordering Information Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Orderi...

Page 27 - Package Diagram

CY7C1546V18, CY7C1557V18CY7C1548V18, CY7C1550V18 Document Number: 001-06550 Rev. *E Page 27 of 28 Package Diagram Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm) ! 0).#/2.%2 ¼ ¼ 8 -#!" -# " ! 8 ¼ -!8 3%!4).'0,!.% ¼ # # 0).#/2.%2 4/06)%7 "/44/-6)%7 " # $ % & ' ( * + , - . 0 2 0 2 + ...

Page 28 - Document History Page; Issue

Document Number: 001-06550 Rev. *E Revised March 11, 2008 Page 28 of 28 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this documentare the trademarks of their respective holders. CY7...