Cypress CY7C1545V18 - Manuals

Cypress CY7C1545V18 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1545V18

Summary

Page 2 - DOFF

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 2 of 28 Logic Block Diagram (CY7C1541V18) Logic Block Diagram (CY7C1556V18) 2M x 8 A rr a y CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Rea d Add. Decode Read Data Reg. RPS WPS Control Logic Add...

Page 4 - Pin Configuration

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 4 of 28 Pin Configuration The pin configuration for CY7C1541V18, CY7C1556V18, CY7C1543V18, and CY7C1545V18 follow. [2] 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1541V18 (8M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ A ...

Page 6 - Pin Definitions; Switching Characteristics

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 6 of 28 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C1541V18 − D [7:0] CY7C1...

Page 8 - Functional Overview; Read Operations; Write Operations; Concurrent Transactions

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 8 of 28 Functional Overview The CY7C1541V18, CY7C1556V18, CY7C1543V18, andCY7C1545V18 are synchronous pipelined burst SRAMsequipped with a read port and a write port. The read port isdedicated to read operations...

Page 9 - to allow the SRAM to adjust its output; Echo Clocks; DLL; Application Example; Figure 1; Figure 1. Application Example; BUS MASTER; DATA IN

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 9 of 28 Depth Expansion The CY7C1543V18 has a port select input for each port. Thisenables for easy depth expansion. Both port selects are sampledon the rising edge of the positive input clock only (K). Each por...

Page 12 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set; IDCODE

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 12 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test AccessPort (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-2001. The TAP ope...

Page 13 - ). The SRAM clock input might not be captured

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 13 of 28 between the TDI and TDO pins and shifts the IDCODE out of thedevice when the TAP controller enters the Shift-DR state. TheIDCODE instruction is loaded into the instruction register atpower up or wheneve...

Page 14 - The state diagram for the TAP controller follows.; TAP Controller State Diagram; RESET

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 14 of 28 The state diagram for the TAP controller follows. [12] TAP Controller State Diagram TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1 0 1 ...

Page 16 - Figure 2

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 16 of 28 TAP AC Switching Characteristics Over the Operating Range [16, 17] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK...

Page 17 - Instruction Codes

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 17 of 28 Identification Register Definitions Instruction Field Value Description CY7C1541V18 CY7C1556V18 CY7C1543V18 CY7C1545V18 Revision Number (31:29) 000 000 000 000 Version number. Cypress Device ID (28:12) ...

Page 18 - Boundary Scan Order; Bump ID; Internal

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 18 of 28 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 ...

Page 19 - Figure 3. Power Up Waveforms; Unstable Clock

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 19 of 28 Power Up Sequence in QDR-II+ SRAM QDR-II+ SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. DuringPower Up, when the DOFF is tied HIGH, the DLL gets lockeda...

Page 20 - DC Electrical Characteristics

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 20 of 28 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Tem...

Page 21 - AC Electrical Characteristics; Capacitance

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 21 of 28 I SB1 Automatic Power down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL f = f MAX = 1/t CYC , Inputs Static 375 MHz x8 525 mA x9 525 x18 525 x36 410 333 MHz x8 500 mA x9 500 x18 ...

Page 22 - Thermal Resistance; ZQ

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 22 of 28 Thermal Resistance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions 165 FBGA Package Unit Θ JA Thermal Resistance(Junction ...

Page 24 - Switching Waveforms; Figure 5. Waveform for 2.0 Cycle Read Latency; WPS

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 24 of 28 Switching Waveforms Read/Write/Deselect Sequence [31, 32, 33] Figure 5. Waveform for 2.0 Cycle Read Latency t KH t KL t CYC t KHKH NOP READ NOP WRITE READ WRITE 1 2 3 4 5 6 7 8 t t t tSA HA SC HC t HD t...

Page 25 - Ordering Information; for actual products offered.

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 25 of 28 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) ...

Page 27 - Package Diagram

CY7C1541V18, CY7C1556V18CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev. *F Page 27 of 28 Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195 ! 0).#/2.%2 ¼ ¼ 8 -#!" -# " ! 8 ¼ -!8 3%!4).'0,!.% ¼ # # 0).#/2.%2 4/06)%7 "/44/-6)%7 " # $ % & ' ( * + , - . ...

Page 28 - Document History Page; ISSUE

Document Number: 001-05389 Rev. *F Revised March 06, 2008 Page 28 of 28 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this documentare the trademarks of their respective holders. CY7...