Cypress CY7C1526V18 - Manuals

Cypress CY7C1526V18 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1526V18

Summary

Page 2 - DOFF

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 2 of 32 Logic Block Diagram (CY7C1511V18) Logic Block Diagram (CY7C1526V18) 2M x 8 A rr a y CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add . Decode Read Data Reg. RPS WPS Control Logic Add...

Page 3 - Array

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 3 of 32 Logic Block Diagram (CY7C1513V18) Logic Block Diagram (CY7C1515V18) CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add. D e cod e Read Data Reg. RPS WPS Control Logic Address Register...

Page 4 - Pin Configuration

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 4 of 32 Pin Configuration The pin configuration for CY7C1511V18, CY7C1526V18, CY7C1513V18, and CY7C1515V18 follow. [1] 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1511V18 (8M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ A ...

Page 6 - Pin Definitions; Application Example

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 6 of 32 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C1511V18 − D [7:0] CY7C...

Page 8 - Functional Overview; Read Operations; Write Operations; Single Clock Mode

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 8 of 32 Functional Overview The CY7C1511V18, CY7C1526V18, CY7C1513V18,CY7C1515V18 are synchronous pipelined Burst SRAMs with aread port and a write port. The read port is dedicated to readoperations and the writ...

Page 9 - to allow the SRAM to adjust its output; Echo Clocks; Switching Characteristics; DLL; AN5062, DLL Considerations in

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 9 of 32 Concurrent Transactions The read and write ports on the CY7C1513V18 operatescompletely independently of one another. As each port latchesthe address inputs on different clock edges, the user can read orw...

Page 10 - Figure 1; Truth Table; ohms; BUS

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 10 of 32 Application Example Figure 1 shows four QDR-II used in an application. Figure 1. Application Example Truth Table The truth table for CY7C1511V18, CY7C1526V18, CY7C1513V18, and CY7C1515V18 follows. [2, 3...

Page 12 - BWS

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 12 of 32 Write Cycle Descriptions The write cycle description table for CY7C1515V18 follows. [2, 10] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments L L L L L–H – During the Data portion of a write sequence, all four bytes...

Page 13 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 13 of 32 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test AccessPort (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-1900. The TAP ope...

Page 14 - and t; ). The SRAM clock input might not be captured

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 14 of 32 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO pins and shifts the IDCODE out of thedevic...

Page 15 - TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 15 of 32 TAP Controller State Diagram The state diagram for the TAP controller follows. [11] TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1 0 1 ...

Page 17 - Figure 2

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 17 of 32 TAP AC Switching Characteristics Over the Operating Range [15, 16] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK...

Page 19 - Boundary Scan Order; Bump ID; Internal

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 19 of 32 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 ...

Page 20 - Power Up Sequence in QDR-II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 20 of 32 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW ...

Page 21 - Maximum Ratings; Operating Range; DC Electrical Characteristics

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 21 of 32 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Tem...

Page 22 - AC Electrical Characteristics

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 22 of 32 I DD [21] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200MHz (x8) 655 mA (x9) 660 (x18) 715 (x36) 850 167MHz (x8) 570 mA (x9) 575 (x18) 615 (x36) 725 I SB1 Automatic Power down C...

Page 23 - Capacitance; Thermal Resistance

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 23 of 32 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD ...

Page 26 - Switching Waveforms

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 26 of 32 Switching Waveforms Figure 5. Read/Write/Deselect Sequence [28, 29, 30] K 1 2 3 4 5 6 7 RPS WPS A Q D C C READ READ WRITE WRITE NOP NOP DON’T CARE UNDEFINED CQ CQ K A0 A1 t KH t KHKH tKL t CYC t tHC tSA...

Page 27 - Ordering Information; for actual products offered.

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 27 of 32 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) ...

Page 30 - Package Diagram

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 30 of 32 Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195 ! 0).#/2.%2 ¼ ¼ 8 -#!" -# " ! 8 ¼ -!8 3%!4).'0,!.% ¼ # # 0).#/2.%2 4/06)%7 "/44/-6)%7 " # $ % & ' ( * + , - . ...

Page 31 - Document History Page; SUBMISSION

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev. *F Page 31 of 32 Document History Page Document Title: CY7C1511V18/CY7C1526V18/CY7C1513V18/CY7C1515V18, 72-Mbit QDR™-II SRAM 4-Word Burst Archi-tectureDocument Number: 38-05363 REV. ECN NO. SUBMISSION DATE ORIG. OF CHAN...