Cypress CY7C1511KV18 - Manuals

Cypress CY7C1511KV18 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1511KV18

Summary

Page 2 - Read; DOFF

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 2 of 31 Logic Block Diagram (CY7C1511KV18) Logic Block Diagram (CY7C1526KV18) 2M x 8 A rra y CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add . Decode Read Data Reg. RPS WPS Control Log...

Page 3 - Array; Deco

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 3 of 31 Logic Block Diagram (CY7C1513KV18) Logic Block Diagram (CY7C1515KV18) CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add. D ecod e Read Data Reg. RPS WPS Control Logic Address Re...

Page 4 - Pin Configuration

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 4 of 31 Pin Configuration The pin configurations for CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1511KV18 (8M x 8) 1 2 3 4 5 6 7 8 9 10...

Page 6 - Pin Definitions; Application Example

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 6 of 31 Pin Definitions Pin Name I/O Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C1511KV18 − D [7:...

Page 8 - Functional Overview; Read Operations; Write Operations

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 8 of 31 Functional Overview The CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, CY7C1515KV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations ...

Page 9 - Switching Characteristics

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 9 of 31 Single Clock Mode The CY7C1511KV18 is used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that...

Page 10 - Figure 1; Truth Table; ohms; BUS

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 10 of 31 Application Example Figure 1 shows four QDR-II used in an application. Figure 1. Application Example Truth Table The truth table for CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 follo...

Page 12 - BWS

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 12 of 31 Write Cycle Descriptions The write cycle description table for CY7C1515KV18 follows. [2, 10] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments L L L L L–H – During the data portion of a write sequence, all four...

Page 13 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 13 of 31 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The ...

Page 15 - TAP Controller State Diagram; The state diagram for the TAP controller follows.

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 15 of 31 TAP Controller State Diagram The state diagram for the TAP controller follows. [11] TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1 0 ...

Page 17 - Figure 2; ALL INPUT PULSES

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 17 of 31 TAP AC Switching Characteristics Over the Operating Range [15, 16] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t T...

Page 19 - Boundary Scan Order; Bump ID; Internal

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 19 of 31 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7...

Page 20 - Power Up Sequence in QDR-II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 20 of 31 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH o...

Page 21 - DC Electrical Characteristics

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 21 of 31 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................. –65°C to +150°CAmbient...

Page 22 - AC Electrical Characteristics

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 22 of 31 I DD [21] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 430 mA (x9) 430 (x18) 440 (x36) 580 167 MHz (x8) 380 mA (x9) 380 (x18) 390 (x36) 510 I SB1 Automatic Power...

Page 23 - Capacitance; Thermal Resistance

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 23 of 31 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, ...

Page 26 - Switching Waveforms

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 26 of 31 Switching Waveforms Figure 5. Read/Write/Deselect Sequence [28, 29, 30] K 1 2 3 4 5 6 7 RPS WPS A Q D C C READ READ WRITE WRITE NOP NOP DON’T CARE UNDEFINED CQ CQ K A0 A1 t KH t KHKH tKL t CYC t tH...

Page 27 - Ordering Information

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 27 of 31 Ordering Information The following table lists all possible speed, package, and temperature range options supported for these devices. Note that some options listed may not be available for order e...

Page 30 - Package Diagram

CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 30 of 31 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±...

Page 31 - Document History Page; Burst Architecture

Document Number: 001-00435 Rev. *E Revised March 30, 2009 Page 31 of 31 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this documentare the trademarks of their respective holders. CY7...