Cypress CY7C1510KV18 - Manuals

Cypress CY7C1510KV18 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1510KV18

Summary

Page 2 - DOFF; DOFF; rray

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 2 of 30 Logic Block Diagram (CY7C1510KV18) Logic Block Diagram (CY7C1525KV18) 4M x 8 A rray CLK A (21:0) Gen. K K Control Logic Address Register D [7:0] Read Add . Decode Read Data Reg. RPS WPS Control Logic...

Page 4 - Pin Configuration

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 4 of 30 Pin Configuration The pin configurations for CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1510KV18 (8M x 8) 1 2 3 4 5 6 7 8 9 10 ...

Page 6 - Pin Definitions; Application Example

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 6 of 30 Pin Definitions Pin Name I/O Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks during valid write operations. CY7C1510KV18 − D [7:0] CY7C152...

Page 8 - Functional Overview; Write Operations

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 8 of 30 Functional Overview The CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operatio...

Page 9 - Echo Clocks; Switching; PLL; Figure 1; Figure 1. Application Example; ohms; BUS

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 9 of 30 Echo Clocks Echo clocks are provided on the QDR-II to simplify data capture on high speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced...

Page 12 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 12 of 30 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The T...

Page 14 - TAP Controller State Diagram; The state diagram for the TAP controller follows.

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 14 of 30 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1 0 1 ...

Page 16 - Figure 2

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 16 of 30 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL...

Page 18 - Boundary Scan Order; Bump ID; Internal

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 18 of 30 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R...

Page 19 - Power Up Sequence in QDR-II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 19 of 30 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or...

Page 20 - DC Electrical Characteristics

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 20 of 30 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................. –65°C to +150°CAmbient ...

Page 21 - AC Electrical Characteristics

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 21 of 30 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 540 mA (x9) 540 (x18) 550 (x36) 660 167 MHz (x8) 480 mA (x9) 480 (x18) 490 (x36) 580 I SB1 Automatic Power ...

Page 22 - Capacitance; Thermal Resistance

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 22 of 30 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V...

Page 23 - Switching Characteristics

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 23 of 30 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consortium Parameter Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max Min Max Min Max t ...

Page 25 - Switching Waveforms; RPS

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 25 of 30 Switching Waveforms Figure 5. Read/Write/Deselect Sequence [26, 27, 28] K 1 2 3 4 5 8 10 6 7 K RPS WPS A D READ READ WRITE WRITE WRITE NOP READ WRITE NOP 9 A0 tKH tKHKH tKL tCYC t tHC tSA tHA tSD tH...

Page 26 - Ordering Information

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 26 of 30 Ordering Information The following table lists all possible speed, package, and temperature range options supported for these devices. Note that some options listed may not be available for order en...

Page 29 - Package Diagram

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18 Document Number: 001-00436 Rev. *E Page 29 of 30 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0...

Page 30 - Document History Page; Architecture

Document Number: 001-00436 Rev. *E Revised March 30, 2009 Page 30 of 30 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this documentare the trademarks of their respective holders. CY7...