Cypress CY7C1472V33 - Manuals

Cypress CY7C1472V33 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1472V33

Summary

Page 2 - Selection Guide; Unit

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 2 of 29 A0, A1, A C MODE CE1CE2CE3 OE READ LOGIC DQsDQP a DQP b DQP c DQP d DQP e DQP f DQP g DQP h D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRIT...

Page 4 - Pin Configurations; TMS

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 4 of 29 Pin Configurations (continued) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d A V DDQ BW d BW a CLK WE V ...

Page 6 - Pin Definitions

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 6 of 29 Pin Definitions Pin Name I/O Type Pin Description A0A1A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK. BW a BW b BW c BW d BW e BW f BW g BW h Input- Sy...

Page 7 - Functional Overview

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 7 of 29 Functional Overview The CY7C1470V33, CY7C1472V33, and CY7C1474V33 aresynchronous-pipelined Burst NoBL SRAMs designed specifi-cally to eliminate wait states during Write/Read transitions. Allsynchronous inputs pass through in...

Page 8 - DD; ZZ Mode Electrical Characteristics

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 8 of 29 On the next clock rise the data presented to DQ and DQP (DQ a,b,c,d,e,f,g,h /DQP a,b,c,d,e,f,g,h for CY7C1474V33, DQ a,b,c,d /DQP a,b,c,d for CY7C1470V33 & DQ a,b /DQP a,b for CY7C1472V33) (or a subset for byte write ope...

Page 9 - Truth Table

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 9 of 29 Notes: 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asse...

Page 10 - Partial Write Cycle Description

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 10 of 29 Partial Write Cycle Description [1, 2, 3, 8] Function (CY7C1470V33) WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ a and DQP a ) L H H H L Write Byte b – (DQ b and DQP b ) L H H ...

Page 11 - Disabling the JTAG Feature; through a pull-up resistor. TDO should be; TAP Controller State Diagram; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 11 of 29 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470V33, CY7C1472V33, and CY7C1474V33incorporates a serial boundary scan test access port (TAP).This port operates in accordance with IEEE Standard1149.1-1990 but does not hav...

Page 12 - ) when the BYPASS instruction is executed.; TAP Instruction Set; plus t

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 12 of 29 Instruction Register Three-bit instructions can be serially loaded into the instructionregister. This register is loaded when it is placed between theTDI and TDO balls as shown in the Tap Controller BlockDiagram. Upon power...

Page 13 - TAP Timing; Test Clock; TAP AC Switching Characteristics

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 13 of 29 possible to capture all other signals and simply ignore thevalue of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data byputting the TAP into the Shift-DR state. ...

Page 14 - Parameter

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 14 of 29 3.3V TAP AC Test Conditions Input pulse levels ................................................ V SS to 3.3V Input rise and fall times ................................................... 1 ns Input timing reference levels ....

Page 18 - Electrical Characteristics

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 18 of 29 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied .....................

Page 20 - Switching Characteristics

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 20 of 29 Switching Characteristics Over the Operating Range [16, 17] Parameter Description –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [18] V CC (typical) to the First Access Read or Write 1 1 1 ms Clock t CYC Clock Cy...

Page 21 - Switching Waveforms

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 21 of 29 Switching Waveforms Read/Write/Timing [22, 23, 24] Notes: 22. For this waveform ZZ is tied LOW.23. When CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 24....

Page 23 - Ordering Information; Commercial

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 23 of 29 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package...

Page 25 - Package Diagrams

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 25 of 29 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LE...

Page 28 - Document History Page; Issue Date

CY7C1470V33CY7C1472V33CY7C1474V33 Document #: 38-05289 Rev. *I Page 28 of 29 Document History Page Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ ArchitectureDocument Number: 38-05289 REV. ECN No. Issue Date Orig. of Change Description...