Cypress CY7C1472BV33 - Manuals

Cypress CY7C1472BV33 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1472BV33

Summary

Page 4 - Pin Configurations

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 4 of 30 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQaDQa V DDQ V SS DQaDQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQdDQd...

Page 5 - TMS

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 5 of 30 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1470BV33 (2M x 36) CY7C1472BV33 (4M x 18) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE...

Page 8 - Functional Overview; Single Read Accesses; Single Read; Single Write Accesses

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 8 of 30 Functional Overview The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33are synchronous-pipelined Burst NoBL SRAMs designed specif-ically to eliminate wait states during read or write transitions. Allsynchronous inputs pa...

Page 9 - Burst Write Accesses; “Single Write Accesses”; Sleep Mode; ZZ Mode Electrical Characteristics

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 9 of 30 access (read, write, or deselect) is latched into the AddressRegister (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP (DQ a,b,c,d /DQP a,b,c,d for CY7C1...

Page 12 - Disabling the JTAG Feature; through a pull up resistor. TDO must be left; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers; Figure 2. TAP Controller State Diagram; Figure 3. TAP Controller Block Diagram

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 12 of 30 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33incorporates a serial boundary scan test access port (TAP). Thisport operates in accordance with IEEE Standard 1149.1-1990but do...

Page 13 - BYPASS instruction is executed.; TAP Instruction Set; “Identification

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 13 of 30 Instruction Register Three-bit instructions can be serially loaded into the instructionregister. This register is loaded when it is placed between the TDIand TDO balls as shown in the “TAP Controller Block Diagram” o...

Page 14 - Figure 4. TAP Timing; T e st Clo ck

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 14 of 30 possible to capture all other signals and simply ignore the valueof the CLK captured in the boundary scan register. After the data is captured, it is possible to shift out the data byputting the TAP into the Shift-DR...

Page 15 - TAP AC Switching Characteristics

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 15 of 30 TAP AC Switching Characteristics Over the Operating Range [9, 10] Parameter Description Min Max Unit Clock t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH time 20 ns t TL TCK Clo...

Page 16 - V TAP AC Output Load Equivalent; T D O; TAP DC Electrical Characteristics And Operating Conditions

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 16 of 30 3.3V TAP AC Test Conditions Input pulse levels ................................................. V SS to 3.3V Input rise and fall times.................................................... 1 ns Input timing reference ...

Page 20 - Electrical Characteristics

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 20 of 30 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature withP...

Page 22 - Switching Characteristics

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 22 of 30 Switching Characteristics Over the Operating Range. Timing reference is 1.5V when V DDQ = 3.3V and is 1.25V when V DDQ = 2.5V. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 21 unless otherwise...

Page 23 - Switching Waveforms; Figure 5

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 23 of 30 Switching Waveforms Figure 5 shows read-write timing waveform. [20, 21, 22] Figure 5. Read/Write Timing WRITE D(A1) 1 2 3 4 5 6 7 8 9 CLK t CYC t CL t CH 10 CE t CEH t CES WE CEN t CENH t CENS BW x ADV/LD t AH t AS A...

Page 24 - Figure 6. NOP, STALL and DESELECT Cycles; Figure 7; Mode Timing

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 24 of 30 Figure 6 shows NOP, STALL and DESELECT Cycles waveform. [20, 21, 23] Figure 6. NOP, STALL and DESELECT Cycles Figure 7 shows ZZ Mode timing waveform. [24, 25] Figure 7. ZZ Mode Timing Switching Waveforms (continued) ...

Page 25 - Ordering Information; for actual products offered.

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 25 of 30 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code ...

Page 27 - Package Diagrams

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *C Page 27 of 30 Package Diagrams Figure 8. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH S...

Page 30 - Document History Page; Issue Date

Document #: 001-15031 Rev. *C Revised February 29, 2008 Page 30 of 30 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in thisdocument may be the trademarks of their respecti...