Cypress CY7C1470V25 - Manuals

Cypress CY7C1470V25 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1470V25

Summary

Page 2 - Selection Guide; Unit

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 2 of 28 A0, A1, A C MODE BW a BW b WE CE1CE2CE3 OE READ LOGIC DQsDQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 WR...

Page 3 - Pin Configurations

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 3 of 28 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQaDQa V DDQ V SS DQaDQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQdDQdDQd V S...

Page 4 - TMS

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 4 of 28 Pin Configurations (continued) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d A V DDQ BW d BW a CLK WE V ...

Page 5 - Pin Name

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 5 of 28 Pin Configurations (continued) A B C D E F G H J K L M N P R T U V W 1 2 3 4 5 6 7 8 9 11 10 DQg DQg DQg DQg DQg DQg DQg DQg DQc DQc DQc DQc NC DQPg DQh DQh DQh DQh DQd DQd DQd DQd DQPd DQPc DQc DQc DQc DQc NC DQh DQh DQh DQ...

Page 6 - Pin Definitions

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 6 of 28 ADV/LD Input- Synchronous Advance/Load Input used to advance the on-chip address counter or load a new address . When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be load...

Page 7 - Functional Overview; Single Read Accesses

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 7 of 28 Functional Overview The CY7C1470V25/CY7C1472V25/CY7C1474V25 aresynchronous-pipelined Burst NoBL SRAMs designed specifi-cally to eliminate wait states during Write/Read transitions. Allsynchronous inputs pass through input re...

Page 8 - DD; ZZ Mode Electrical Characteristics

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 8 of 28 CY7C1474V25, BW a,b,c,d for CY7C1470V25 and BW a,b for CY7C1472V25) inputs must be driven in each cycle of theburst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Ass...

Page 9 - Partial Write Cycle Description

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 9 of 28 Partial Write Cycle Description [1, 2, 3, 8] Function (CY7C1470V25) WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ a and DQP a ) L H H H L Write Byte b – (DQ b and DQP b ) L H H L...

Page 10 - Disabling the JTAG Feature; through a pull-up resistor. TDO should be; TAP Controller State Diagram; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 10 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470V25/CY7C1472V25/CY7C1474V25 incorpo-rates a serial boundary scan test access port (TAP). This portoperates in accordance with IEEE Standard 1149.1-1990 butdoes not have th...

Page 11 - ) when the BYPASS instruction is executed.; TAP Instruction Set; plus t

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 11 of 28 Instruction Register Three-bit instructions can be serially loaded into the instructionregister. This register is loaded when it is placed between theTDI and TDO balls as shown in the Tap Controller BlockDiagram. Upon power...

Page 12 - TAP Timing; Test Clock; TAP AC Switching Characteristics

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 12 of 28 possible to capture all other signals and simply ignore thevalue of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data byputting the TAP into the Shift-DR state. ...

Page 13 - TDO

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 13 of 28 2.5V TAP AC Test Conditions Input pulse levels ................................................ V SS to 2.5V Input rise and fall time ..................................................... 1 ns Input timing reference levels ...

Page 14 - Scan Register Sizes; Register Name; Identification Codes; Instruction

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 14 of 28 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order–165FBGA 71 52 – Boundary Scan Order–209BGA – – 110 Identification Codes Instructi...

Page 17 - Electrical Characteristics

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 17 of 28 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied .....................

Page 19 - Switching Characteristics

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 19 of 28 Switching Characteristics Over the Operating Range [15, 16] Parameter Description –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [17] V CC (typical) to the First Access Read or Write 1 1 1 ms Clock t CYC Clock Cy...

Page 20 - Switching Waveforms

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 20 of 28 Switching Waveforms Read/Write/Timing [21, 22, 23] Notes: 21. For this waveform ZZ is tied LOW.22. When CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH,CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 23. ...

Page 22 - Ordering Information; Commercial

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 22 of 28 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package...

Page 24 - Package Diagrams

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 24 of 28 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LE...

Page 27 - Document History Page; Issue Date

CY7C1470V25CY7C1472V25CY7C1474V25 Document #: 38-05290 Rev. *I Page 27 of 28 Document History Page Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit(2M x 36/4M x 18/1M x 72)Pipelined SRAM with NoBL™ ArchitectureDocument Number: 38-05290 REV. ECN No. Issue Date Orig. of Change Description o...