Cypress CY7C1464AV33 - Manuals

Cypress CY7C1464AV33 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1464AV33

Summary

Page 2 - Selection Guide; Unit; Maximum Access Time

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 2 of 27 A0, A1, A C MODE BW a BW b WE CE1CE2CE3 OE READ LOGIC DQsDQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2...

Page 3 - Pin Configurations

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 3 of 27 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQaDQa V DDQ V SS DQaDQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQdDQdDQd ...

Page 4 - TMS

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 4 of 27 Pin Configurations (continued) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/72M V DDQ BW d BW a C...

Page 5 - Pin Definitions; Pin Name

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 5 of 27 Pin Definitions Pin Name I/O Type Pin Description A0A1A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK. BW a BW b BW c BW d BW e BW f BW g BW h Input-...

Page 7 - Functional Overview; Single Read Accesses

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 7 of 27 Functional Overview The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 aresynchronous-pipelined Burst NoBL SRAMs designed specifi-cally to eliminate wait states during Write/Read transitions. Allsynchronous inputs pass through in...

Page 8 - DD; ZZ Mode Electrical Characteristics

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 8 of 27 counter is incremented. The correct BW (BW a,b,c,d,e,f,g,h for CY7C1464AV33, BW a,b,c,d for CY7C1460AV33 and BW a,b for CY7C1462AV33) inputs must be driven in each cycle of theburst write in order to write the correct byt...

Page 10 - Disabling the JTAG Feature; through a pull-up resistor. TDO should be; TAP Controller State Diagram; Performing a TAP Reset; Instruction Register

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 10 of 27 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 incor-porates a serial boundary scan test access port (TAP). Thispart is fully compliant with 1149.1. The TAP operates usingJEDEC-standar...

Page 11 - ) when the BYPASS instruction is executed.; TAP Instruction Set; and t

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 11 of 27 When the TAP controller is in the Capture-IR state, the twoleast significant bits are loaded with a binary “01” pattern toallow for fault isolation of the board-level serial test data path. Bypass Register To save time w...

Page 12 - Reserved; TAP Timing; Test Clock

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 12 of 27 When this scan cell, called the “extest output bus tri-state,” islatched into the preload register during the “Update-DR” statein the TAP controller, it will directly control the state of theoutput (Q-bus) pins, when the...

Page 14 - Scan Register Sizes; Register Name; Identification Codes; Instruction

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 14 of 27 Scan Register Sizes Register Name Bit Size (×36) Bit Size (×18) Bit Size (×72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order (165-ball FBGA package) 89 89 - Boundary Scan Order (209-ball FBGA package) - ...

Page 15 - 65-ball FBGA Boundary Scan Order; ball ID; Internal

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 15 of 27 165-ball FBGA Boundary Scan Order [13] CY7C1460AV33 (1M x 36), CY7C1462AV33 (2M x 18) Bit# ball ID Bit# ball ID Bit# ball ID Bit# ball ID 1 N6 26 E11 51 A3 76 N1 2 N7 27 D11 52 A2 77 N2 3 10N 28 G10 53 B2 78 P1 4 P11 29 ...

Page 16 - 09-ball BGA Boundary Scan Order; Ball ID

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 16 of 27 209-ball BGA Boundary Scan Order [13, 14] CY7C14604V33 (512K x 72) Bit# Ball ID Bit# ball ID Bit# ball ID Bit# ball ID 1 W6 36 6F 71 6H 106 3K 2 V6 37 8K 72 6C 107 4K 3 U6 38 9K 73 6B 108 6K 4 W7 39 10K 74 6A 109 2K 5 V7...

Page 17 - Electrical Characteristics

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 17 of 27 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ..................

Page 18 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 18 of 27 Note: 17. Tested initially and after any design or process changes that may affect these parameters. Capacitance [17] Parameter Description Test Conditions 100 TQFP Max. 165 FBGA Max. 209 FBGA Max. Unit C IN Input Capaci...

Page 19 - Switching Characteristics

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 19 of 27 Switching Characteristics Over the Operating Range [22, 23] Parameter Description –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [18] V CC (typical) to the first access read or write 1 1 1 ms Clock t CYC Clock...

Page 20 - Switching Waveforms

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 20 of 27 Switching Waveforms Read/Write/Timing [24, 25, 26] Notes: 24. For this waveform ZZ is tied low.25. When CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH,CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 2...

Page 22 - Ordering Information; Commercial

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 22 of 27 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Pack...

Page 24 - Package Diagrams

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 24 of 27 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY...

Page 27 - Document History Page; Issue Date

CY7C1460AV33CY7C1462AV33CY7C1464AV33 Document #: 38-05353 Rev. *D Page 27 of 27 Document History Page Document Title: CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ ArchitectureDocument Number: 38-05353 REV. ECN No. Issue Date Orig. of Change Des...