Cypress CY7C1464AV25 - Manuals

Cypress CY7C1464AV25 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1464AV25

Summary

Page 2 - Selection Guide; Unit

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 2 of 27 Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Access Time 2.6 3.2 3.4 ns Maximum Operating Current 435 385 335 mA Maximum CMOS Standby Current 120 120 120 mA A0, A1, A C MODE BW a BW b WE CE1CE2CE3 OE READ LOGIC DQ...

Page 3 - Pin Configurations

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 3 of 27 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQaDQa V DDQ V SS DQaDQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQdDQdDQd ...

Page 4 - TMS

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 4 of 27 Pin Configurations (continued) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/72M V DDQ BW d BW a C...

Page 6 - Pin Definitions

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 6 of 27 CE 1 Input- Synchronous Chip Enable 1 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with CE 2 and CE 3 to select/deselect the device. CE 2 Input- Synchronous Chip Enable 2 Input, active HIGH ....

Page 7 - Functional Overview; Single Read Accesses

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 7 of 27 Functional Overview The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 aresynchronous-pipelined Burst NoBL SRAMs designed specifi-cally to eliminate wait states during Write/Read transitions. Allsynchronous inputs pass through in...

Page 8 - DD; ZZ Mode Electrical Characteristics

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 8 of 27 CY7C1460AV25, BW a,b,c,d for CY7C1460AV25 and BW a,b for CY7C1462AV25) inputs must be driven in each cycle of theburst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous inpu...

Page 9 - Partial Write Cycle Description

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 9 of 27 Partial Write Cycle Description [1, 2, 3, 8] Function (CY7C1460AV25) WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ a and DQP a ) L H H H L Write Byte b – (DQ b and DQP b ) L H...

Page 10 - Disabling the JTAG Feature; ) to prevent clocking of the device. TDI and TMS are; TAP Controller State Diagram; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers; Instruction Register

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 10 of 27 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 incor-porates a serial boundary scan test access port (TAP). Thispart is fully compliant with 1149.1. The TAP operates usingJEDEC-standar...

Page 11 - ) when the BYPASS instruction is executed.; TAP Instruction Set; and t

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 11 of 27 When the TAP controller is in the Capture-IR state, the twoleast significant bits are loaded with a binary “01” pattern toallow for fault isolation of the board-level serial test data path. Bypass Register To save time w...

Page 12 - Reserved; TAP Timing; Test Clock; TAP AC Switching Characteristics

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 12 of 27 When this scan cell, called the “extest output bus tri-state,” islatched into the preload register during the “Update-DR” statein the TAP controller, it will directly control the state of theoutput (Q-bus) pins, when the...

Page 13 - TDO

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 13 of 27 2.5V TAP AC Test Conditions Input pulse levels ............................................... V SS to 2.5V Input rise and fall time .................................................... 1 ns Input timing reference levels...

Page 14 - Scan Register Sizes; Register Name; Identification Codes; Instruction

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 14 of 27 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order (165-ball FBGA package) 89 89 – Boundary Scan Order (209-ball FBGA package) – ...

Page 15 - 65-ball FBGA Boundary Scan Order; Ball ID; Internal

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 15 of 27 165-ball FBGA Boundary Scan Order [12] CY7C1460AV25 (1M x 36), CY7C1462AV25 (2M x 18) Bit# Ball ID Bit# Ball ID Bit# Ball ID Bit# Ball ID 1 N6 26 E11 51 A3 76 N1 2 N7 27 D11 52 A2 77 N2 3 N10 28 G10 53 B2 78 P1 4 P11 29 ...

Page 16 - 09-ball FBGA Boundary Scan Order

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 16 of 27 209-ball FBGA Boundary Scan Order [12, 13] CY7C1464AV25 (512K x 72) Bit# Ball ID Bit# Ball ID Bit# Ball ID Bit# Ball ID 1 W6 36 F6 71 H6 106 K3 2 V6 37 K8 72 C6 107 K4 3 U6 38 K9 73 B6 108 K6 4 W7 39 K10 74 A6 109 K2 5 V...

Page 17 - Electrical Characteristics

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 17 of 27 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ..................

Page 18 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 18 of 27 Capacitance [16] Parameter Description Test Conditions 100 TQFP Max. 165 FBGA Max. 209 FBGA Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 2.5V V DDQ = 2.5V 6.5 7 5 pF C CLK Clock Input Capacitance 3 7 5 ...

Page 19 - Switching Characteristics

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 19 of 27 Switching Characteristics Over the Operating Range [21, 22] Parameter Description –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [17] V CC (typical) to the first access read or write 1 1 1 ms Clock t CYC Clock...

Page 20 - Switching Waveforms; NOP, STALL and DESELECT Cycles

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 20 of 27 Switching Waveforms Read/Write/Timing [23, 24, 25] NOP, STALL and DESELECT Cycles [23, 24, 26] Notes: 23. For this waveform ZZ is tied low.24. When CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH,CE...

Page 22 - Ordering Information; Commercial

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 22 of 27 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Pack...

Page 24 - Package Diagrams

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 24 of 27 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY...

Page 27 - Document History Page; Issue Date

CY7C1460AV25CY7C1462AV25CY7C1464AV25 Document #: 38-05354 Rev. *D Page 27 of 27 Document History Page Document Title: CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 36-Mbit (1-Mbit x 36/2-Mbit x 18/512K x 72) Pipelined SRAM with NoBL™ ArchitectureDocument Number: 38-05354 REV. ECN No. Issue Date Orig. of Ch...