Cypress CY7C1446AV33 - Manuals

Cypress CY7C1446AV33 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1446AV33

Summary

Page 4 - Pin Configurations

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 4 of 31 Pin Configurations DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQc V DDQ V SSQ DQ C DQ C DQ C DQ C V...

Page 5 - TMS

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 5 of 31 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1440AV33 (1M x 36) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE2 DQ C DQ D...

Page 7 - Pin Definitions

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 7 of 31 CE 2 Input- Synchronous Chip Enable 2 Input, active HIGH . Sampled on the rising edge of CLK. Used in conjunction with CE 1 and CE 3 to select/deselect the device. CE 2 is sampled only when a new external address is loade...

Page 8 - Functional Overview; Single Read Accesses

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 8 of 31 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. All data outputs pass throughoutput registers controlled by the rising edge of the clock.Maximum access de...

Page 9 - DD; ZZ Mode Electrical Characteristics

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 9 of 31 Interleaved Burst Address Table (MODE = Floating or V DD ) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (...

Page 11 - Disabling the JTAG Feature; TAP Controller State Diagram; GW

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 11 of 31 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 incor-porates a serial boundary scan test access port (TAP). Thispart is fully compliant with IEEE Standard 1149.1. The TAPoperates using...

Page 12 - Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers; ) when the BYPASS instruction is executed.; TAP Instruction Set; and t; or to the selection of another boundary scan test operation.

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 12 of 31 Performing a TAP Reset A RESET is performed by forcing TMS HIGH (V DD ) for five rising edges of TCK. This RESET does not affect the operationof the SRAM and may be performed while the SRAM isoperating. At power-up, the ...

Page 13 - TAP Timing; Test Clock

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 13 of 31 The shifting of data for the SAMPLE and PRELOAD phasescan occur concurrently when required—that is, while datacaptured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in...

Page 14 - TAP AC Switching Characteristics; TDO

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 14 of 31 3.3V TAP AC Test Conditions Input pulse levels ............................................... V SS to 3.3V Input rise and fall times ...................... ..............................1ns Input timing reference levels...

Page 17 - 09-ball FBGA Boundary Scan Order; ball ID; Internal

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 17 of 31 Note: 16. Bit# 138 is preset HIGH. 209-ball FBGA Boundary Scan Order [14, 16] CY7C1446AV33 (512K x 72) Bit # ball ID Bit # ball ID Bit # ball ID Bit # ball ID 1 W6 36 F6 71 H6 106 K3 2 V6 37 K8 72 C6 107 K4 3 U6 38 K9 73...

Page 18 - Electrical Characteristics

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 18 of 31 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ..................

Page 19 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 19 of 31 Capacitance [19] Parameter Description Test Conditions 100 TQFP Max. 165 FBGA Max. 209 FBGA Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 6.5 7 5 pF C CLK Clock Input Capacitance 3 7 ...

Page 20 - Switching Characteristics

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 20 of 31 Switching Characteristics Over the Operating Range [24, 25] Parameter Description –250 –200 –167 Unit Min. Max Min. Max. Min. Max t POWER V DD (Typical) to the first Access [20] 1 1 1 ms Clock t CYC Clock Cycle Time 4.0 ...

Page 21 - Switching Waveforms; Read Cycle Timing

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 21 of 31 Switching Waveforms Read Cycle Timing [26] Note: 26. On this diagram, when CE is LOW: CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. tCYC t CL CLK ADSP t ADH t AD...

Page 22 - Write Cycle Timing

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 22 of 31 Write Cycle Timing [26, 27] Note: 27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW X LOW. Switching Waveforms (continued) t CYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A...

Page 23 - Read/Write Cycle Timing

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 23 of 31 Read/Write Cycle Timing [26, 28, 29] Notes: 28. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC. 29. GW is HIGH. Switching Waveforms (continued) tCYC tCL ...

Page 24 - ZZ Mode Timing; CLK

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 24 of 31 ZZ Mode Timing [30, 31] Notes: 30. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.31. DQs are in high-Z when exiting ZZ sleep mode....

Page 25 - Ordering Information; Commercial

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 25 of 31 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Pack...

Page 27 - Package Diagrams

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 27 of 31 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY...

Page 30 - Document History Page; SRAM

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 30 of 31 Document History Page Document Title: CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Document Number: 38-05383 REV. ECN NO. Issue Date Orig. of Change Description of Change...

Page 31 - Changed t; from 5 ns to 10 ns in TAP

CY7C1440AV33CY7C1442AV33CY7C1446AV33 Document #: 38-05383 Rev. *E Page 31 of 31 *E 473650 See ECN VKN Added the Maximum Rating for Supply Voltage on V DDQ Relative to GND. Changed t TH , t TL from 25 ns to 20 ns and t TDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table.Updated the Orde...