Cypress CY7C144 - Manuals - manualsarea.com

Page 2 - Pin Configurations

CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 2 of 21 Pin Configurations Figure 1. 68-Pin PLCC (Top View) Figure 2. 64-Pin PLCC (Top View) 1011121314151617181920 21222324 67 60595857565554535251504948 3132 33 34 35 36 37 38 39 40 41 42 43 5 4 3 2 1 68 66 65 64 63 62 61 A A 4L A 3L A 2L A 1L A 0...

Page 4 - Electrical Characteristics

CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 4 of 21 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. [5] Storage Temperature ..................................... − 65 ° C to +150 ° C Ambient Temperature with Power Appli...

Page 5 - Capacitance

CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 5 of 21 Electrical Characteristics Over the Operating Range (continued) Parameter Description Test Conditions 7C144-35 7C145-35 7C144-55 7C145-55 Unit Min Max Min Max V OH Output HIGH Voltage V CC = Min., I OH = − 4.0 mA 2.4 2.4 V V OL Output LOW Vo...

Page 6 - Switching Characteristics

CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 6 of 21 Figure 4. AC Test Loads and Waveforms 3.0V GND 90% 90% 10% ≤ 3 ns ≤ 3 ns 10% ALL INPUT PULSES (a) Normal Load (Load1) 5V OUTPUT C = 30 pF V TH = 1.4V OUTPUT C = 30pF (b) Th évenin Equivalent (Load 1) (c) Three-State Delay (Load 3) C = 30 pF ...

Page 8 - Switching Waveforms

CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 8 of 21 Switching Waveforms Figure 5. Read Cycle No. 1 (Either Port Address Access) [15, 16] Figure 6. Read Cycle No. 2 (Either Port CE/OE Access) [15, 17, 18] Figure 7. Read Timing with Port-to-Port Delay (M/S=L) [19, 20] Notes 15. R/W is HIGH for ...

Page 12 - CE

CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 12 of 21 Figure 14. Busy Timing Diagram No. 1 (CE Arbitration) [29] Figure 15. Busy Timing Diagram No. 2 (Address Arbitration) [29] Note: 29. If t PS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee o...

Page 13 - Figure 16. Interrupt Timing Diagrams; Left Side Sets INT

CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 13 of 21 Figure 16. Interrupt Timing Diagrams Notes 30. t HA depends on which enable pin (CE L or R/W L ) is deasserted first. 31. t INS or t INR depends on which enable pin (CE L or R/W L ) is asserted last. Switching Waveforms (continued) WRITE 1F...

Page 14 - Write Operation; Figure 8; Read Operation; Table 4; Busy; Table 5

CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 14 of 21 Architecture The CY7C144/5 consists of a an array of 8K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any locatio...

Page 16 - Figure 17. Typical DC and AC Characteristics

CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 16 of 21 Figure 17. Typical DC and AC Characteristics 1.4 1.0 0.4 4.0 4.5 5.0 5.5 6.0 − 55 25 125 1.2 1.0 120 80 0 1.0 2.0 3.0 4.0 OUT P UT SOUR CE CURR EN T (mA) SUPPLY VOLTAGE (V) NORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE NORMALIZED SUPPLY CURRE...

Page 17 - Ordering Information

CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 17 of 21 Ordering Information 8K x8 Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15 CY7C144-15AC A65 64-Pin Thin Quad Flat Pack Commercial CY7C144-15AXC A65 64-Pin Pb-Free Thin Quad Flat Pack CY7C144-15JC J81 68-...

Page 19 - Package Diagrams

CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 19 of 21 Package Diagrams Figure 18. 64-Pin Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 (51-85046) 51-85046-*C [+] Feedback

Page 21 - Worldwide Sales and Design Support; Change

Document #: 38-06034 Rev. *D Revised December 10, 2008 Page 21 of 21 All products and company names mentioned in this document may be the trademarks of their respective holders. CY7C145, CY7C144 © Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change wit...