Cypress CY7C1425JV18 - Manuals

Cypress CY7C1425JV18 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1425JV18

Summary

Page 2 - DOFF; DOFF

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 2 of 26 Logic Block Diagram (CY7C1410JV18) Logic Block Diagram (CY7C1425JV18) 2M x 8 A rr a y CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Rea d Add. Decode Read Data Reg. RPS WPS Control Logic Ad...

Page 3 - Array

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 3 of 26 Logic Block Diagram (CY7C1412JV18) Logic Block Diagram (CY7C1414JV18) 1M x 18 Arra y CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add . Decode Read Data Reg. RPS WPS Control Logic Ad...

Page 4 - Pin Configuration

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 4 of 26 Pin Configuration The pin configuration for CY7C1410JV18, CY7C1412JV18, and CY7C1414JV18 follow. [1] 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1410JV18 (4M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A WPS...

Page 6 - Pin Definitions; Application Example

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 6 of 26 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. CY7C1410JV18 - D [7:0] CY7C1425JV18 -...

Page 8 - Functional Overview; Write Operations

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 8 of 26 Functional Overview The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, andCY7C1414JV18 are synchronous pipelined Burst SRAMs with aread port and a write port. The read port is dedicated to readoperations and t...

Page 9 - Programmable Impedance; to allow the SRAM to adjust its output; Echo Clocks; Switching Characteristics; DLL; Figure 1; Figure 1. Application Example; ohms; BUS

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 9 of 26 Programmable Impedance An external resistor, RQ, must be connected between the ZQ pinon the SRAM and V SS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of t...

Page 12 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 12 of 26 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test AccessPort (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-2001. The TAP oper...

Page 13 - and t; ). The SRAM clock input might not be captured

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 13 of 26 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO pins and shifts the IDCODE out of thedevice...

Page 14 - TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 14 of 26 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1 0 1 0 ...

Page 16 - Figure 2

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 16 of 26 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK ...

Page 18 - Boundary Scan Order; Bump ID; Internal

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 18 of 26 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 1...

Page 19 - Power Up Sequence in QDR-II SRAM; Power Up Sequence; Power Up Waveforms

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 19 of 26 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. DuringPower Up, when the DOFF is tied HIGH, the DLL gets lockedafte...

Page 20 - Maximum Ratings; Operating Range; DC Electrical Characteristics

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 20 of 26 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temp...

Page 21 - AC Electrical Characteristics; Capacitance

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 21 of 26 AC Electrical Characteristics Over the Operating Range [11] Parameter Description Test Conditions Min Typ Max Unit V IH Input HIGH Voltage V REF + 0.2 – – V V IL Input LOW Voltage – – V REF – 0.2 V Capac...

Page 23 - Switching Waveforms; RPS

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 23 of 26 Switching Waveforms Figure 3. Read/Write/Deselect Sequence [25, 26, 27] K 1 2 3 4 5 8 10 6 7 K RPS WPS A D READ READ WRITE WRITE WRITE NOP READ WRITE NOP 9 A0 tKH tKHKH tKL tCYC t tHC tSA tHA tSD tHD SC ...

Page 24 - Ordering Information; for actual products offered.

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 24 of 26 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) O...

Page 25 - Package Diagram

CY7C1410JV18, CY7C1425JV18CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev. *D Page 25 of 26 Package Diagram Figure 4. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 1.40 MAX. SEATING PLANE ...

Page 26 - Document History Page; ISSUE

Document #: 001-12561 Rev. *D Revised March 10, 2007 Page 26 of 26 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this documentare the trademarks of their respective holders. CY7C1410...