Cypress CY7C1415JV18 - Manuals

Cypress CY7C1415JV18 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1415JV18

Summary

Page 2 - DOFF

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 2 of 28 Logic Block Diagram (CY7C1411JV18) Logic Block Diagram (CY7C1426JV18) 1M x 8 A rr a y CLK A (19:0) Gen. K K Control Logic Address Register D [7:0] Read Add . Decode Read Data Reg. RPS WPS Control Lo...

Page 3 - rray

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 3 of 28 Logic Block Diagram (CY7C1413JV18) Logic Block Diagram (CY7C1415JV18) CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add. D e cod e Read Data Reg. RPS WPS Control Logic Address R...

Page 4 - Pin Configuration

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 4 of 28 Pin Configuration The pin configuration for CY7C1411JV18, CY7C1413JV18, and CY7C1415JV18 follows. [1] 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1411JV18 (4M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72...

Page 6 - Pin Definitions

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 6 of 28 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C1411JV18 − D [7:0...

Page 8 - Functional Overview; Read Operations; Write Operations; Single Clock Mode

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 8 of 28 Functional Overview The CY7C1411JV18, CY7C1426JV18, CY7C1413JV18, andCY7C1415JV18 are synchronous pipelined burst SRAMs with aread port and a write port. The read port is dedicated to readoperations...

Page 9 - to allow the SRAM to adjust its output; Echo Clocks; Switching Characteristics; DLL; DLL Considerations in; Application Example; Figure 1; Figure 1. Application Example; ohms; BUS

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 9 of 28 includes forwarding data from a write cycle that was initiated onthe previous K clock rise. Read accesses and write access must be scheduled such thatone transaction is initiated on any clock cycle....

Page 12 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 12 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test AccessPort (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-2001. The TA...

Page 13 - and t; ). The SRAM clock input might not be captured

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 13 of 28 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO pins and shifts the IDCODE out of the...

Page 14 - TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 14 of 28 TAP Controller State Diagram The state diagram for the TAP controller follows. [11] TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1...

Page 16 - Figure 2

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 16 of 28 TAP AC Switching Characteristics Over the Operating Range [15, 16] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t T...

Page 18 - Boundary Scan Order; Bump ID; Internal

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 18 of 28 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7...

Page 19 - Power Up Sequence in QDR-II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 19 of 28 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or...

Page 20 - Maximum Ratings; Operating Range; DC Electrical Characteristics

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 20 of 28 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambien...

Page 21 - AC Electrical Characteristics

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 21 of 28 I SB1 Automatic Power Down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL f = f MAX = 1/t CYC , Inputs Static 300 MHz (x8) 350 mA (x9) 350 (x18) 355 (x36) 395 250 MHz (x8) 355...

Page 22 - Capacitance; Thermal Resistance

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 22 of 28 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, ...

Page 24 - Switching Waveforms

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 24 of 28 Switching Waveforms Figure 5. Read/Write/Deselect Sequence [27, 28, 29] K 1 2 3 4 5 6 7 RPS WPS A Q D C C READ READ WRITE WRITE NOP NOP DON’T CARE UNDEFINED CQ CQ K A0 A1 t KH t KHKH tKL t CYC t tH...

Page 25 - Ordering Information; for actual products offered.

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 25 of 28 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed ...

Page 27 - Package Diagram

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 27 of 28 Package Diagram Figure 6. 165-Ball FBGA (15 x 17 x 1.40 mm), 51-85195 ! 0).#/2.%2 ¼ ¼ 8 -#!" -# " ! 8 ¼ -!8 3%!4).'0,!.% ¼ # # 0).#/2.%2 4/06)%7 "/44/-6)%7 " # $ % & ' ( * + ...

Page 28 - Document History Page; ISSUE

Document Number: 001-12557 Rev. *C Revised June 25, 2008 Page 28 of 28 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this documentare the trademarks of their respective holders. CY7C...