Cypress CY7C1393CV18 - Manuals

Cypress CY7C1393CV18 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1393CV18

Summary

Page 2 - Re; CQ; x 8 Array; rite Add; CQ; x 9 Arra

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 2 of 30 Logic Block Diagram (CY7C1392CV18) Logic Block Diagram (CY7C1992CV18) 1M x 8 Array CLK A (19:0) Gen. K K Control Logic Address Register D [7:0] Re ad Add. Decode Read Data Reg. LD Q [7:0] Reg. Reg. Reg. 8...

Page 3 - Read; cod

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 3 of 30 Logic Block Diagram (CY7C1393CV18) Logic Block Diagram (CY7C1394CV18) 512 K x 18 Array CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. LD Q [17:0] Reg. Reg. R...

Page 4 - Pin Configuration

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 4 of 30 Pin Configuration The Pin Configuration for CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 follows. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1392CV18 (2M x 8) 1 2 3 4 5 6 7 8 9 10 11 A ...

Page 6 - Pin Definitions; Application Example

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 6 of 30 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data input signals. Sampled on the rising edge of K and K clocks during valid write operations. CY7C1392CV18 - D [7:0] CY7C1992CV18 -...

Page 8 - Functional Overview; Write Operations

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 8 of 30 Functional Overview The CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, andCY7C1394CV18 are synchronous pipelined Burst SRAMsequipped with a DDR-II Separate IO interface, which operateswith a read latency of on...

Page 9 - Switching Characteristics; DLL; DLL Considerations in QDRIITM/DDRII; Figure 1; Figure 1. Application Example

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 9 of 30 synchronized to the output clock of the DDR-II. In the single clockmode, CQ is generated with respect to K and CQ is generatedwith respect to K. The timing for the echo clocks is shown in Switching Charac...

Page 12 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 12 of 30 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test AccessPort (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-2001. The TAP oper...

Page 13 - and t; ). The SRAM clock input might not be captured

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 13 of 30 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO pins and shifts the IDCODE out of thedevice...

Page 14 - TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 14 of 30 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1 0 1 0 ...

Page 16 - Figure 2; ALL INPUT PULSES

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 16 of 30 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK ...

Page 18 - Boundary Scan Order; Bump ID; Internal

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 18 of 30 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 2J 1 6P 29 9G 57 5B 85 3K 2 6N 30 11F 58 5A 86 3J 3 7P 31 11G 59 4A 87 2K 4 7N 32 9F 60 5C 88 1K 5 7R 33 1...

Page 19 - Power Up Sequence in DDR-II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 19 of 30 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (...

Page 20 - Maximum Ratings; Operating Range; DC Electrical Characteristics

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 20 of 30 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temp...

Page 21 - AC Electrical Characteristics

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 21 of 30 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 575 mA (x9) 575 (x18) 600 (x36) 630 167 MHz (x8) 485 mA (x9) 490 (x18) 500 (x36) 540 I SB1 Automatic Power Down ...

Page 22 - Capacitance; Thermal Resistance

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 22 of 30 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD =...

Page 25 - Switching Waveforms; LD; NOP

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 25 of 30 Switching Waveforms Figure 5. Read/Write/Deselect Sequence [27, 28, 29] K 1 2 3 4 5 6 7 8 K LD R/W A Q D C C# READ(burst of 2) READ(burst of 2) READ(burst of 2) WRITE(burst of 2) WRITE(burst of 2) t KHCH...

Page 26 - Ordering Information; for actual products offered.

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 26 of 30 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) ...

Page 29 - Package Diagram

CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev. *C Page 29 of 30 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0.05 0...

Page 30 - Document History Page; Submission

Document #: 001-07162 Rev. *C Revised May 22, 2008 Page 30 of 30 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this documentare the trademarks of their respective holders. CY7C1392CV...