Cypress CY7C1387FV25 - Manuals

Cypress CY7C1387FV25 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1387FV25

Summary

Page 3 - Pin Configurations

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 3 of 30 Pin Configurations A A A A A 1 A 0 NC /7 2 M NC /3 6 M V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ...

Page 5 - TMS

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 5 of 30 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1386DV25 (512K x 36) 2 3 4 5 6 7 1 ABCD E F G H J K L M N P R TDO NC/288MNC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C B...

Page 6 - Pin Definitions

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 6 of 30 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address inputs used to select one of the address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, ...

Page 8 - Interleaved Burst Address Table

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 8 of 30 The write signals (GW, BWE, and BW X ) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles tocomplete. If GW is asserted LOW on the second clock...

Page 11 - Disabling the JTAG Feature; ) to prevent clocking of the device. TDI and TMS are; through a pull up resistor.; TAP Controller State Diagram; TAP; TAP Controller Block Diagram; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 11 of 30 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/CY7C1387FV25 incorporates a serial boundary scan testaccess port (TAP).This part is fully compliant with 1149.1. Th...

Page 12 - . Upon power up, the instruction register is loaded; ) when the BYPASS instruction is executed.; TAP Instruction Set; . Three of these instructions are listed as

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 12 of 30 Instruction Register Three-bit instructions can be serially loaded into the instructionregister. This register is loaded when it is placed between theTDI and TDO balls as shown in the TAP Controller...

Page 13 - TAP Timing; Test Clock

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 13 of 30 The shifting of data for the SAMPLE and PRELOAD phasescan occur concurrently when required; that is, while datacaptured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS i...

Page 14 - TDO; TAP DC Electrical Characteristics And Operating Conditions

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 14 of 30 TAP AC Test Conditions Input pulse levels .................................................V SS to 2.5V Input rise and fall time..................................................... 1 nsInput timing...

Page 16 - 19-Ball BGA Boundary Scan Order; Ball ID; Internal

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 16 of 30 119-Ball BGA Boundary Scan Order [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 G4 67 L1 2 T4 24 E7 46 A4 68 M2 3 T5 25 D7 47 G3 69 N1 4 T6 26 H7 48 C3 70 P1 5 R5 27 ...

Page 17 - 65-Ball BGA Boundary Scan Order

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 17 of 30 165-Ball BGA Boundary Scan Order [14, 16] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9...

Page 18 - Electrical Characteristics

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 18 of 30 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested.Storage Temperature ................................. –65 ° C to +150 ° C Ambi...

Page 20 - Switching Characteristics

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 20 of 30 Switching Characteristics Over the Operating Range [20, 21] Parameter Description 250 MHz 200 MHz 167 MHz Unit Min. Max. Min. Max. Min. Max. t POWER V DD (Typical) to the first Access [22] 1 1 1 ms ...

Page 21 - Switching Waveforms; Read Cycle Timing

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 21 of 30 Switching Waveforms Read Cycle Timing [26] tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES GW, BWE,BW Data Out (DQ) High-Z tDOH tCO ADV t OEHZ t CO Single READ BURST READ tOE...

Page 22 - Write Cycle Timing

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 22 of 30 Write Cycle Timing [26, 27] Switching Waveforms (continued) t CYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE, BW X ADV BURST READ BURST WRITE D(A2) D(A2 + 1) D(A3) D(A3 +...

Page 23 - Read/Write Cycle Timing

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 23 of 30 Read/Write Cycle Timing [26, 28, 29] Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A2 tCEH tCES Data Out (Q) High-Z ADV Single WRITE D(A3) A4 A5 A6 D(A5)...

Page 24 - ZZ Mode Timing; CLK

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 24 of 30 ZZ Mode Timing [30, 31] Switching Waveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes 30. Device m...

Page 25 - Ordering Information

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 25 of 30 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (...

Page 26 - visit

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 26 of 30 250 CY7C1386DV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial CY7C1387DV25-250AXCCY7C1386FV25-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C138...

Page 27 - Package Diagrams

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 27 of 30 Package Diagrams Figure 1. 100-Pin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUS...

Page 30 - Document History Page; DCD Sync SRAM

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 30 of 30 Document History Page Document Title: CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM Document Number: 38-05548 REV. ECN NO. Issue Date Orig....